PA linearization using multi-stage look-up-table predistorter with optimal linear weighted delay

Zhao Yang*, Qin Zhang, Gaofeng Xia, Jiong Liu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Citation (Scopus)

Abstract

A digital predistortion linearization algorithm using multi-stage look-up-table (LUT) predistorter with optimal linear weighted delay is proposed for memory power amplifiers (PA). In order to find the optimal linear delay weight under the constraint of fewer stages of LUTs which is imposed by the limited hardware resources, minimum normalized mean-square error (MNMSE) is chosen as the criterion. The new algorithm adopts the reference model indirect learning architecture, and updates its LUTs using LMS algorithm without training sequences. The multi-stage LUT predistorter has the simple structure of finite-impulse-response filter, which involves less computational complexity and is easy for hardware implementation. By evaluating optimal linear delay weight, the new algorithm achieves better linearization results. Excellent performance of the new algorithm is validated by results from hardware tests.

Original languageEnglish
Title of host publicationICSP 2012 - 2012 11th International Conference on Signal Processing, Proceedings
Pages47-51
Number of pages5
DOIs
Publication statusPublished - 2012
Event2012 11th International Conference on Signal Processing, ICSP 2012 - Beijing, China
Duration: 21 Oct 201225 Oct 2012

Publication series

NameInternational Conference on Signal Processing Proceedings, ICSP
Volume1

Conference

Conference2012 11th International Conference on Signal Processing, ICSP 2012
Country/TerritoryChina
CityBeijing
Period21/10/1225/10/12

Keywords

  • Digital predistortion
  • Look-up-table
  • Memory effect
  • Power amplifier linearization
  • Weighted delay

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