Abstract
Signal Temporal Logic (STL) is a formal language used for specifying and reasoning about the temporal properties of signals in a system. It provides a framework for expressing complex temporal behaviors and requirements in a concise and expressive manner. However, the main limitation of the current use of STL languages for describing machine tasks is that the construction of STL languages is still stuck on manual generation. Therefore, in this paper, we build a model for transforming logic natural language to STL formulas with a substantial increase in accuracy and inference speed, compared to the previous translation approach. Firstly, we pre-train a large language model (llama2) for logical ability, then we archive unsupervised learning with randomly generated STL language as a dataset and instruction fine-tuning on NL-STL pairs. Finally, we achieve an excellent result comparing to the work before.
Original language | English |
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Pages (from-to) | 469-474 |
Number of pages | 6 |
Journal | Proceedings of the IEEE International Conference on Cybernetics and Intelligent Systems, CIS |
Issue number | 2024 |
DOIs | |
Publication status | Published - 2024 |
Event | 11th IEEE International Conference on Cybernetics and Intelligent Systems and 11th IEEE International Conference on Robotics, Automation and Mechatronics, CIS-RAM 2024 - Hangzhou, China Duration: 8 Aug 2024 → 11 Aug 2024 |
Keywords
- Llama2
- LLM
- NL translation
- NL-STL