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Network properties and latency of triple-based hierarchical interconnection netrwork

  • Baojun Qiao*
  • , Feng Shi
  • , Wedxing Ji
  • , Hong Song
  • *Corresponding author for this work
  • Beijing Institute of Technology
  • Henan University

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A new chip design paradigm called Network on Chip (NOC) offers a promising architectural choice for future SOC (System-on-Chip). Triple-based Hierarchical Interconnection Network (THIN) was proposed that aims to decrease the node degree, reduce the links and shorten the diameter. The topology of THIN is very simple and it has obviously hierarchical, symmetric and scalable characteristic. In this paper, the network properties and zero-load latency are studied and compared with 2-D mesh. The compare results show that THIN is a better candidate for constructing the NOC than 2-D Mesh, when there are not too many nodes.

Original languageEnglish
Title of host publication2007 IEEE International Conference on Control and Automation, ICCA
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages976-979
Number of pages4
ISBN (Print)1424408180, 9781424408184
DOIs
Publication statusPublished - 2007
Event2007 IEEE International Conference on Control and Automation, ICCA - Guangzhou, China
Duration: 30 May 20071 Jun 2007

Publication series

Name2007 IEEE International Conference on Control and Automation, ICCA

Conference

Conference2007 IEEE International Conference on Control and Automation, ICCA
Country/TerritoryChina
CityGuangzhou
Period30/05/071/06/07

Keywords

  • Interconnection architecture
  • Network properties
  • Network topology
  • Network-on-chip

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