Multiple regular expression matching hardware architecture

Multiple regular expression matching has become one of the most important performance bottlenecks in network security applications. The paper presents a hardware-based multiple regular expressions matching architecture with a four-stage pipeline. The architecture simultaneously matches multiple regular expressions. The algorithm splits the regular expressions into strings and constrained repetitions and then utilizes a string matching architecture for the strings and a hardware circuit for the constrained repetitions. Experiments show that the architecture can achieve a high throughput of 1.9 Gb/s using Virtex2 devices and 2.1 Gb/s using Virtex4 devices. This solution supports more regular expressions with less storage than other architectures.