TY - JOUR
T1 - Low-Latency and Area-Efficient Elliptic Curve Point Multiplication Architectures Over Koblitz Curves
AU - Jiang, Yujie
AU - Zhang, Jingqi
AU - Wang, An
AU - Hao, Yue
AU - Wang, Jiawei
AU - Chen, Zhiming
AU - Zhu, Liehuang
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2025
Y1 - 2025
N2 - Point multiplication is the core operation in elliptic curve cryptography. Koblitz curves are a special class of curves that can utilize the Frobenius mapping to accelerate the implementation of point multiplication operations. For point multiplication on Koblitz curves, this paper first proposes an optimized tNAF scalar conversion algorithm along with its corresponding hardware architecture. Additionally, for the computation of point multiplication, this paper proposes two optimal computational architectures: an area-efficient architecture and a low-latency architecture, both of which achieve the highest pipeline efficiency. The area-efficient architecture adopts a compact four-stage pipeline with a single multiplier, ensuring high circuit area utilization efficiency while achieving relatively low computation latency. The low-latency architecture implements two-stage and three-stage pipeline designs respectively in different binary fields, using two multipliers to reduce the clock cycles for point addition and further decrease the computation latency. The proposed architectures were implemented on Virtex-7 FPGA. For the GF(2163), GF(2283), and GF(2571) fields, the latency for the area-efficient architecture are 1.683μs, 3.455μs and 7.511μs, with slices usage of 3631, 7867 and 20612, and the point multiplication latency for the low-latency architecture are 1.347μs, 3.279μs and 7.071μs, with slices usage of 6026, 14246 and 38515. A comparison with state-of-the-art designs shows that the proposed point multiplication architectures offer significant advantages in terms of performance. In the GF(2163) field, the computation latency of the area-efficient architecture and the low-latency architecture is reduced by at least 21.158% and 43.952%, respectively. And in the GF(2283) field, the reduction in latency is 38.985% and 42.459%, while in the GF(2571) field, the reduction in latency is 58.111% and 59.720%.
AB - Point multiplication is the core operation in elliptic curve cryptography. Koblitz curves are a special class of curves that can utilize the Frobenius mapping to accelerate the implementation of point multiplication operations. For point multiplication on Koblitz curves, this paper first proposes an optimized tNAF scalar conversion algorithm along with its corresponding hardware architecture. Additionally, for the computation of point multiplication, this paper proposes two optimal computational architectures: an area-efficient architecture and a low-latency architecture, both of which achieve the highest pipeline efficiency. The area-efficient architecture adopts a compact four-stage pipeline with a single multiplier, ensuring high circuit area utilization efficiency while achieving relatively low computation latency. The low-latency architecture implements two-stage and three-stage pipeline designs respectively in different binary fields, using two multipliers to reduce the clock cycles for point addition and further decrease the computation latency. The proposed architectures were implemented on Virtex-7 FPGA. For the GF(2163), GF(2283), and GF(2571) fields, the latency for the area-efficient architecture are 1.683μs, 3.455μs and 7.511μs, with slices usage of 3631, 7867 and 20612, and the point multiplication latency for the low-latency architecture are 1.347μs, 3.279μs and 7.071μs, with slices usage of 6026, 14246 and 38515. A comparison with state-of-the-art designs shows that the proposed point multiplication architectures offer significant advantages in terms of performance. In the GF(2163) field, the computation latency of the area-efficient architecture and the low-latency architecture is reduced by at least 21.158% and 43.952%, respectively. And in the GF(2283) field, the reduction in latency is 38.985% and 42.459%, while in the GF(2571) field, the reduction in latency is 58.111% and 59.720%.
KW - Elliptic Curve Cryptography (ECC)
KW - Field-Programmable Gate Arrays (FPGA)
KW - Koblitz
KW - Point Multiplication
UR - http://www.scopus.com/inward/record.url?scp=105002854450&partnerID=8YFLogxK
U2 - 10.1109/JIOT.2025.3562194
DO - 10.1109/JIOT.2025.3562194
M3 - Article
AN - SCOPUS:105002854450
SN - 2327-4662
JO - IEEE Internet of Things Journal
JF - IEEE Internet of Things Journal
ER -