Low-Complexity Parallel Architecture for Joint Matched Filtering and Timing Recovery in Terahertz Communications

Research output: Contribution to journalArticlepeer-review

Abstract

Emerging intelligent transportation systems are driving demand for ultra-fast and reliable wireless communication, pushing physical-layer design toward millimeter-wave (mmWave) and terahertz (THz) bands. However, as critical components of the receiver, conventional matched filtering (MF) and timing recovery (TR) incur high complexity and latency, limiting their applicability in such high-throughput scenarios. To address this, we propose a feedback-based unified parallel architecture for joint MF and TR (PAMT), which integrates timing error compensation into the MF process. PAMT flexibly supports different timing error detection algorithms, such as Oerder & Meyr or Gardner algorithms, to accommodate varying latency and precision requirements. It is optimized for 4x oversampling systems and can be easily generalized to other configurations. Simulations demonstrate the effectiveness and low complexity of PAMT, which is further validated by a hardware implementation on a Xilinx XCVU9P FPGA under 220 GHz, 64QAM, 15 Gbps, and 64-way parallelism, confirming its feasibility for THz communication systems.

Original languageEnglish
Pages (from-to)1-6
Number of pages6
JournalIEEE Transactions on Vehicular Technology
DOIs
Publication statusAccepted/In press - 2026
Externally publishedYes

Keywords

  • FPGA
  • Matched filtering
  • Parallel architecture
  • THz communications
  • Timing recovery

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