TY - GEN
T1 - Lightweight NPU Method Based on Hyper-Threading Technology
AU - Zhang, Ao
AU - Li, Yongrui
AU - Li, Wenlong
AU - Xie, Yizhuang
AU - Zhang, Zhihan
AU - Yang, Zhu
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - With the rapid development of deep learning, the processing power of Neural Processing Unit(NPU) continues to improve. However, this leads to an increasing scale of logical resources for NPU, making it challenging to deploy NPU on Field-Programmable Gate Array(FPGA). To address this issue and enable the deployment of high-computational-power NPU on FPGA, this paper proposes a lightweight NPU method based on hyper-threading technology, considering the characteristics of NPU hardware architecture. This method effectively reduces the logical resources usage of the NPU while ensuring only a minimal decrease in computational power, thus enabling successful FPGA deployment. The overall experiment is based on the Virtex UltraScale+ HBM VCU128 FPGA platform. After testing, it was found that the NPU, previously undeployable, could be successfully deployed after lightweight processing. The resource usage ratio of LUTs decreased by about 10%, and the computational power only decreased by 4%. In other words, by using this method, the scale of logical resource usage of the NPU was effectively reduced while ensuring a minimal decrease in computational power, improving the deployment situation of the NPU on FPGA. This approach has certain reference value and significance for the lightweight design of NPU.
AB - With the rapid development of deep learning, the processing power of Neural Processing Unit(NPU) continues to improve. However, this leads to an increasing scale of logical resources for NPU, making it challenging to deploy NPU on Field-Programmable Gate Array(FPGA). To address this issue and enable the deployment of high-computational-power NPU on FPGA, this paper proposes a lightweight NPU method based on hyper-threading technology, considering the characteristics of NPU hardware architecture. This method effectively reduces the logical resources usage of the NPU while ensuring only a minimal decrease in computational power, thus enabling successful FPGA deployment. The overall experiment is based on the Virtex UltraScale+ HBM VCU128 FPGA platform. After testing, it was found that the NPU, previously undeployable, could be successfully deployed after lightweight processing. The resource usage ratio of LUTs decreased by about 10%, and the computational power only decreased by 4%. In other words, by using this method, the scale of logical resource usage of the NPU was effectively reduced while ensuring a minimal decrease in computational power, improving the deployment situation of the NPU on FPGA. This approach has certain reference value and significance for the lightweight design of NPU.
KW - FPGA
KW - Hyper-threading Technology
KW - Lightweighting
KW - NPU
UR - http://www.scopus.com/inward/record.url?scp=86000015015&partnerID=8YFLogxK
U2 - 10.1109/ICSIDP62679.2024.10869015
DO - 10.1109/ICSIDP62679.2024.10869015
M3 - Conference contribution
AN - SCOPUS:86000015015
T3 - IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2024
BT - IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2nd IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2024
Y2 - 22 November 2024 through 24 November 2024
ER -