Key techniques of VHDL parser's automatic generation

VHDL and its supporting environment are an active domain in the field of logic design. In this paper the design principle and some key techniques to solve the problems on the implementation of the VHDL parser are introduced. According to the methods discussed in the paper, the VHDL parser based on VHDL IEEE 1076 standard version is implemented and a series of strict tests are done. This VHDL parser is a front-end tool of the VHDL high level synthesis and the mixed level simulation system developed by the Research Center of ASIC of BIT.