Investigation on repetitive UIS reliability of SiC MOSFETs with varied JFET region width

— This study fabricated six groups of 1200 V planar-gate SiC MOSFETs with varying JFET region widths. Single-pulse unclamped inductive switching testing was first performed to evaluate ultimate avalanche capability, revealing that JFET width exerts negligible influence on single-pulse avalanche tolerance, with the exception of the 1.8 μm group which exhibited anomalies potentially associated with process-induced variations. Subsequently, repetitive UIS stress was applied to monitor the evolution of key electrical parameters with cycling. Combined with TCAD simulation results, the analysis indicates that for narrow JFET devices, highly concentrated avalanche current and heat cause thermal fatigue in contact metals and field oxide degradation, ultimately leading to gate-source short-circuit failure; conversely, for wide JFET devices, diminished electric field shielding by the P-well facilitates hot carrier injection into the gate oxide under high electric fields, generating numerous traps that eventually form conductive leakage paths. This study provides design guidance for JFET region optimization in high-reliability SiC power devices.