Instruction scheduling algorithm for register file connectivity clustered VLIW architecture

Generally VLIW (Very Long Instruction Word) processors are implemented as bus-connectivity clustered architecture, in which the function units in a cluster only access the corresponding local registers and different clusters are connected by buses. This architecture can avoid aggressive growing of delay, area and power in full-connectivity VLIW processors when function units increase. However, performance degradation is induced by its copy operations and latency of communications between clusters. This paper presents a new clustered architecture, in which a register file is used to connect all the clusters so as to turn copy and latency away. This paper also gives instruction scheduling algorithm to improve the performance. The experimental results indicate that this new architecture under the help of this scheduling algorithm shows only 13% performance degradation and little code size increase in average compared with those of fully connectivity VLIW architecture, which prevails that of bus-connectivity clustered VLIW architecture.