Influence of transistors with BTI-induced aging on SRAM write performance

Write time is a critical component of memory performance, which often defines cycle time. In order to accurately predict static random access memory (SRAM) performance, it is also important to take temporal degradation effects into account. This paper investigates the influence of bias temperature instability induced transistor degradation on a dynamic write performance of 20 nm bulk CMOS SRAM. The circuit simulations are based on the comprehensive physical simulation of the aging process and on a very accurate statistical compact model extraction and generation technology. Several scenarios, which differ based on aging pattern of the cell, are investigated to identify the most important transistors and the corresponding critical aging conditions. Mismatch between the two inverters results in an imbalance of the cell, which enlarges the difference in write time between 0 and 1. Finally, we show a response surface of changes in write margin in response to different degradation levels in the ON and OFF transistors.