Improving the performance of adaptive cache in reconfigurable VLIW processor

Sensen Hu; Anthony Brandon; Qi Guo; Yizhuo Wang

doi:10.1007/978-3-319-56258-2_1

Improving the performance of adaptive cache in reconfigurable VLIW processor

Sensen Hu^*
, Anthony Brandon
, Qi Guo
, Yizhuo Wang

^*Corresponding author for this work

School of Computer Science and Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Citations (Scopus)

Abstract

In this paper, we study the impact of cache reconfiguration on the cache misses when the issue-width of a VLIW processor is changed. We clearly note here that our investigation pertains the local temporal effects of the cache resizing and how we counteract the negative impact of cache misses in such resizing instances. We propose a novel reconfigurable d-cache framework that can dynamically adapt its least recently used (LRU) replacement policy without much hardware overhead. We demonstrate that using our adaptive d-cache, it ensures a smooth cache performance from one cache size to the other. This approach is orthogonal to future research in cache resizing for such architectures that take into account energy consumption and performance of the overall application.

Original language	English
Title of host publication	Applied Reconfigurable Computing - 13th International Symposium, ARC 2017, Proceedings
Editors	Antonio Carlos Beck, Luigi Carro , Stephan Wong, Koen Bertels
Publisher	Springer Verlag
Pages	3-15
Number of pages	13
ISBN (Print)	9783319562575
DOIs	https://doi.org/10.1007/978-3-319-56258-2_1
Publication status	Published - 2017
Event	13th International Symposium on Applied Reconfigurable Computing, ARC 2017 - Delft, Netherlands Duration: 3 Apr 2017 → 7 Apr 2017

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	10216 LNCS
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	13th International Symposium on Applied Reconfigurable Computing, ARC 2017
Country/Territory	Netherlands
City	Delft
Period	3/04/17 → 7/04/17

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Cache
Cache resizing
Downsizing
Issue-width
Reconfiguration
VLIW
ρ-VEX

Access to Document

10.1007/978-3-319-56258-2_1

Cite this

Hu, S., Brandon, A., Guo, Q., & Wang, Y. (2017). Improving the performance of adaptive cache in reconfigurable VLIW processor. In A. C. Beck, L. Carro , S. Wong, & K. Bertels (Eds.), Applied Reconfigurable Computing - 13th International Symposium, ARC 2017, Proceedings (pp. 3-15). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 10216 LNCS). Springer Verlag. https://doi.org/10.1007/978-3-319-56258-2_1

Hu, Sensen ; Brandon, Anthony ; Guo, Qi et al. / Improving the performance of adaptive cache in reconfigurable VLIW processor. Applied Reconfigurable Computing - 13th International Symposium, ARC 2017, Proceedings. editor / Antonio Carlos Beck ; Luigi Carro ; Stephan Wong ; Koen Bertels . Springer Verlag, 2017. pp. 3-15 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

@inproceedings{d649f8da0164412b839eb5bd082db130,

title = "Improving the performance of adaptive cache in reconfigurable VLIW processor",

abstract = "In this paper, we study the impact of cache reconfiguration on the cache misses when the issue-width of a VLIW processor is changed. We clearly note here that our investigation pertains the local temporal effects of the cache resizing and how we counteract the negative impact of cache misses in such resizing instances. We propose a novel reconfigurable d-cache framework that can dynamically adapt its least recently used (LRU) replacement policy without much hardware overhead. We demonstrate that using our adaptive d-cache, it ensures a smooth cache performance from one cache size to the other. This approach is orthogonal to future research in cache resizing for such architectures that take into account energy consumption and performance of the overall application.",

keywords = "Cache, Cache resizing, Downsizing, Issue-width, Reconfiguration, VLIW, ρ-VEX",

author = "Sensen Hu and Anthony Brandon and Qi Guo and Yizhuo Wang",

note = "Publisher Copyright: {\textcopyright} Springer International Publishing AG 2017.; 13th International Symposium on Applied Reconfigurable Computing, ARC 2017 ; Conference date: 03-04-2017 Through 07-04-2017",

year = "2017",

doi = "10.1007/978-3-319-56258-2\_1",

language = "English",

isbn = "9783319562575",

series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

publisher = "Springer Verlag",

pages = "3--15",

editor = "Beck, \{Antonio Carlos\} and \{Carro \}, Luigi and Stephan Wong and \{Bertels \}, Koen",

booktitle = "Applied Reconfigurable Computing - 13th International Symposium, ARC 2017, Proceedings",

address = "Germany",

}

Hu, S, Brandon, A, Guo, Q & Wang, Y 2017, Improving the performance of adaptive cache in reconfigurable VLIW processor. in AC Beck, L Carro , S Wong & K Bertels (eds), Applied Reconfigurable Computing - 13th International Symposium, ARC 2017, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 10216 LNCS, Springer Verlag, pp. 3-15, 13th International Symposium on Applied Reconfigurable Computing, ARC 2017, Delft, Netherlands, 3/04/17. https://doi.org/10.1007/978-3-319-56258-2_1

Improving the performance of adaptive cache in reconfigurable VLIW processor. / Hu, Sensen; Brandon, Anthony; Guo, Qi et al.
Applied Reconfigurable Computing - 13th International Symposium, ARC 2017, Proceedings. ed. / Antonio Carlos Beck; Luigi Carro ; Stephan Wong; Koen Bertels . Springer Verlag, 2017. p. 3-15 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 10216 LNCS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Improving the performance of adaptive cache in reconfigurable VLIW processor

AU - Hu, Sensen

AU - Brandon, Anthony

AU - Guo, Qi

AU - Wang, Yizhuo

N1 - Publisher Copyright: © Springer International Publishing AG 2017.

PY - 2017

Y1 - 2017

N2 - In this paper, we study the impact of cache reconfiguration on the cache misses when the issue-width of a VLIW processor is changed. We clearly note here that our investigation pertains the local temporal effects of the cache resizing and how we counteract the negative impact of cache misses in such resizing instances. We propose a novel reconfigurable d-cache framework that can dynamically adapt its least recently used (LRU) replacement policy without much hardware overhead. We demonstrate that using our adaptive d-cache, it ensures a smooth cache performance from one cache size to the other. This approach is orthogonal to future research in cache resizing for such architectures that take into account energy consumption and performance of the overall application.

AB - In this paper, we study the impact of cache reconfiguration on the cache misses when the issue-width of a VLIW processor is changed. We clearly note here that our investigation pertains the local temporal effects of the cache resizing and how we counteract the negative impact of cache misses in such resizing instances. We propose a novel reconfigurable d-cache framework that can dynamically adapt its least recently used (LRU) replacement policy without much hardware overhead. We demonstrate that using our adaptive d-cache, it ensures a smooth cache performance from one cache size to the other. This approach is orthogonal to future research in cache resizing for such architectures that take into account energy consumption and performance of the overall application.

KW - Cache

KW - Cache resizing

KW - Downsizing

KW - Issue-width

KW - Reconfiguration

KW - VLIW

KW - ρ-VEX

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U2 - 10.1007/978-3-319-56258-2_1

DO - 10.1007/978-3-319-56258-2_1

M3 - Conference contribution

AN - SCOPUS:85017555276

SN - 9783319562575

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 3

EP - 15

BT - Applied Reconfigurable Computing - 13th International Symposium, ARC 2017, Proceedings

A2 - Beck, Antonio Carlos

A2 - Carro , Luigi

A2 - Wong, Stephan

A2 - Bertels , Koen

PB - Springer Verlag

T2 - 13th International Symposium on Applied Reconfigurable Computing, ARC 2017

Y2 - 3 April 2017 through 7 April 2017

ER -

Hu S, Brandon A, Guo Q, Wang Y. Improving the performance of adaptive cache in reconfigurable VLIW processor. In Beck AC, Carro L, Wong S, Bertels K, editors, Applied Reconfigurable Computing - 13th International Symposium, ARC 2017, Proceedings. Springer Verlag. 2017. p. 3-15. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-319-56258-2_1

Improving the performance of adaptive cache in reconfigurable VLIW processor

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

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