FPGA implementation of 3 bit block adaptive quantization algorithm

Using field programmable gate array (FPGA) for synthesized aperture radar (SAR) data compression can reduce the time of data compression, so it increases the resolution of radar. Under studying the block adaptive quantization (BAQ) algorithm and comparing the hardware structure of digital signal processor (DSP) and FPGA, the idea of using FPGA for BAQ is presented in this paper, and the detail processes of 3 bit BAQ compression implemented by FPGA are also introduced. Experimental results show that implementing BAQ compression employing FPGA has the advantages of high speed, simple circuit structure and high signal fidelity after quantization. So using application specific integrated circuit (ASIC) for SAR raw data compression will become one of efficient approaches for improving speed.