TY - GEN
T1 - FPGA Design and Implementation of ECG Classification Neural Network
AU - Lu, Tiantai
AU - Zhao, Bowen
AU - Xie, Min
AU - Ma, Zhifeng
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - The multi-label classification algorithm of electrocardiogram can be applied in clinical diagnosis as an aid. By porting the algorithm to intelligent terminal devices, it can monitor the health of patients in real-time and provide disease warnings, allowing for the timely detection of potential cardiovascular diseases in users. In this paper, a lightweight multi-scale attention network is designed, and a multi-channel parallel accelerator based on output data reuse is developed specifically for this network. The accelerator adopts a deep pipeline parallel architecture, which can highly reuse data in time and space, making it suitable for deploying on hardware platforms with limited resources. The accelerator designed in this paper is deployed on Xilinx's ZYNQ-7100 hardware platform, achieving a throughput of 116.7 GOPs with a power consumption of 6. 67W, and has a hardware resource utilization rate of 0.33 GOPS/DSP and 2.85 GOPS/kLUT. Compared with general CPUs/GPUs, this accelerator has greater advantages in terms of hardware utilization efficiency and energy consumption, which meets the requirements of low-power and high-performance for intelligent terminal devices.
AB - The multi-label classification algorithm of electrocardiogram can be applied in clinical diagnosis as an aid. By porting the algorithm to intelligent terminal devices, it can monitor the health of patients in real-time and provide disease warnings, allowing for the timely detection of potential cardiovascular diseases in users. In this paper, a lightweight multi-scale attention network is designed, and a multi-channel parallel accelerator based on output data reuse is developed specifically for this network. The accelerator adopts a deep pipeline parallel architecture, which can highly reuse data in time and space, making it suitable for deploying on hardware platforms with limited resources. The accelerator designed in this paper is deployed on Xilinx's ZYNQ-7100 hardware platform, achieving a throughput of 116.7 GOPs with a power consumption of 6. 67W, and has a hardware resource utilization rate of 0.33 GOPS/DSP and 2.85 GOPS/kLUT. Compared with general CPUs/GPUs, this accelerator has greater advantages in terms of hardware utilization efficiency and energy consumption, which meets the requirements of low-power and high-performance for intelligent terminal devices.
KW - ECG
KW - FPGA (Field Programmable Gate Array)
KW - accelerator
KW - classification
KW - hardware
KW - multi-scale attention network
UR - http://www.scopus.com/inward/record.url?scp=85169295564&partnerID=8YFLogxK
U2 - 10.1109/CCAI57533.2023.10201313
DO - 10.1109/CCAI57533.2023.10201313
M3 - Conference contribution
AN - SCOPUS:85169295564
T3 - 2023 IEEE 3rd International Conference on Computer Communication and Artificial Intelligence, CCAI 2023
SP - 85
EP - 91
BT - 2023 IEEE 3rd International Conference on Computer Communication and Artificial Intelligence, CCAI 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 3rd IEEE International Conference on Computer Communication and Artificial Intelligence, CCAI 2023
Y2 - 26 May 2023 through 28 May 2023
ER -
