FPGA-based accelerator for convolution operations

Yunfei Cao; Xin Wei; Tingting Qiao; He Chen

doi:10.1109/ICSIDP47821.2019.9172934

FPGA-based accelerator for convolution operations

Yunfei Cao
, Xin Wei
, Tingting Qiao
, He Chen

Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Citations (Scopus)

Abstract

Convolutional neural networks have been widely used in many deep learning applications. Convolutional neural networks have a large number of convolution operations, which poses a huge challenge to real-time performance. In recent years, FPGA implementations of convolutional accelerators have received much attention due to their high performance and energy efficiency. In this paper, we implement an accelerator for convolution operations through the systolic array architecture on Xilinx ZedBoard device. The experimental results show that ours designed accelerators achieving performance density of up to 0.032 Gop/s/DSP.

Original language	English
Title of host publication	ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728123455
DOIs	https://doi.org/10.1109/ICSIDP47821.2019.9172934
Publication status	Published - Dec 2019
Event	2019 IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2019 - Chongqing, China Duration: 11 Dec 2019 → 13 Dec 2019

Publication series

Name	ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019

Conference

Conference	2019 IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2019
Country/Territory	China
City	Chongqing
Period	11/12/19 → 13/12/19

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Accelerator
CNN
FPGA
Systolic Array

Access to Document

10.1109/ICSIDP47821.2019.9172934

Cite this

Cao, Y., Wei, X., Qiao, T., & Chen, H. (2019). FPGA-based accelerator for convolution operations. In ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019 Article 9172934 (ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICSIDP47821.2019.9172934

@inproceedings{1be94e1acc2d499e8121dafeec7c7098,

title = "FPGA-based accelerator for convolution operations",

abstract = "Convolutional neural networks have been widely used in many deep learning applications. Convolutional neural networks have a large number of convolution operations, which poses a huge challenge to real-time performance. In recent years, FPGA implementations of convolutional accelerators have received much attention due to their high performance and energy efficiency. In this paper, we implement an accelerator for convolution operations through the systolic array architecture on Xilinx ZedBoard device. The experimental results show that ours designed accelerators achieving performance density of up to 0.032 Gop/s/DSP.",

keywords = "Accelerator, CNN, FPGA, Systolic Array",

author = "Yunfei Cao and Xin Wei and Tingting Qiao and He Chen",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2019 ; Conference date: 11-12-2019 Through 13-12-2019",

year = "2019",

month = dec,

doi = "10.1109/ICSIDP47821.2019.9172934",

language = "English",

series = "ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019",

address = "United States",

}

Cao, Y, Wei, X, Qiao, T & Chen, H 2019, FPGA-based accelerator for convolution operations. in ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019., 9172934, ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2019, Chongqing, China, 11/12/19. https://doi.org/10.1109/ICSIDP47821.2019.9172934

FPGA-based accelerator for convolution operations. / Cao, Yunfei; Wei, Xin; Qiao, Tingting et al.
ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 9172934 (ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - FPGA-based accelerator for convolution operations

AU - Cao, Yunfei

AU - Wei, Xin

AU - Qiao, Tingting

AU - Chen, He

PY - 2019/12

Y1 - 2019/12

N2 - Convolutional neural networks have been widely used in many deep learning applications. Convolutional neural networks have a large number of convolution operations, which poses a huge challenge to real-time performance. In recent years, FPGA implementations of convolutional accelerators have received much attention due to their high performance and energy efficiency. In this paper, we implement an accelerator for convolution operations through the systolic array architecture on Xilinx ZedBoard device. The experimental results show that ours designed accelerators achieving performance density of up to 0.032 Gop/s/DSP.

AB - Convolutional neural networks have been widely used in many deep learning applications. Convolutional neural networks have a large number of convolution operations, which poses a huge challenge to real-time performance. In recent years, FPGA implementations of convolutional accelerators have received much attention due to their high performance and energy efficiency. In this paper, we implement an accelerator for convolution operations through the systolic array architecture on Xilinx ZedBoard device. The experimental results show that ours designed accelerators achieving performance density of up to 0.032 Gop/s/DSP.

KW - Accelerator

KW - CNN

KW - FPGA

KW - Systolic Array

UR - https://www.scopus.com/pages/publications/85091932417

U2 - 10.1109/ICSIDP47821.2019.9172934

DO - 10.1109/ICSIDP47821.2019.9172934

M3 - Conference contribution

AN - SCOPUS:85091932417

T3 - ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019

BT - ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2019 IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2019

Y2 - 11 December 2019 through 13 December 2019

ER -

Cao Y, Wei X, Qiao T, Chen H. FPGA-based accelerator for convolution operations. In ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 9172934. (ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019). doi: 10.1109/ICSIDP47821.2019.9172934

FPGA-based accelerator for convolution operations

Abstract

Publication series

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UN SDGs

Keywords

Access to Document

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