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Ferroelectric-Polarization-Modulated 2D Floating-Gate Memory Enabling a 106 On/Off Ratio under ±1 V Gate-Voltage Sweep

  • Tianze Yu
  • , Ce Li
  • , Weili Zhen
  • , Dongliang Yang
  • , Zirui Zhang
  • , Huihan Li
  • , Yutao Li
  • , Ruitong Bie
  • , Mingyue Yuan
  • , Linfeng Sun*
  • *Corresponding author for this work
  • Beijing Institute of Technology

Research output: Contribution to journalLetterpeer-review

Abstract

Floating-gate transistors based on 2D materials have attracted great interest owing to their superior memory characteristics and high reliability. However, most reported devices still suffer from high operating voltages, limited multifunctionality, etc. Here, we proposed a ferroelectric-polarization-modulated floating-gate transistor (FMFGT) based on a CIPS/MLG/hBN/MoS2 van der Waals heterostructure. The switchable and stable ferroelectric polarization of CIPS effectively reduces the tunneling barrier, exhibiting an on/off ratio (>106) when the sweep voltage is reduced to 1 V. In addition, the FMFGT exhibits robust dynamic response under an ultrafast pulse (∼20 ns) and achieves a maximum on/off ratio exceeding 109. Furthermore, the device demonstrates controllable synaptic plasticity under diverse stimuli, facilitating the integration of multiple optoelectronic logic gates. This work provides new insights into the role of ferroelectric polarization in floating-gate devices and establishes a promising solution toward low-voltage, multifunctional memories in edge computing and artificial intelligence.

Original languageEnglish
Pages (from-to)7554-7563
Number of pages10
JournalNano Letters
Volume26
Issue number23
DOIs
Publication statusPublished - 17 Jun 2026
Externally publishedYes

Keywords

  • ferroelectric polarization
  • floating-gate memory
  • optoelectronic synapses
  • van der Waals heterostructure

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