Fama: An FPGA-Oriented Multiscalar Multiplication Accelerator Optimized via Algorithm-Hardware Co-Design

Yan Xu; Jingqi Zhang; Xiyan Dong; An Wang; Xinghua Wang; Liehuang Zhu

doi:10.1109/TCAD.2025.3608005

Fama: An FPGA-Oriented Multiscalar Multiplication Accelerator Optimized via Algorithm-Hardware Co-Design

Yan Xu
, Jingqi Zhang^*
, Xiyan Dong
, An Wang
, Xinghua Wang
, Liehuang Zhu

^*Corresponding author for this work

Hunan University
Beijing Institute of Technology

Research output: Contribution to journal › Article › peer-review

Abstract

Multiscalar multiplication (MSM) is the primary computational bottleneck in zero-knowledge proof (ZKP) protocols. To address this, we introduce Fama, a field-programmable gate array (FPGA)-oriented MSM accelerator developed through algorithm-hardware co-optimization. By integrating a 3D-Pippenger optimization algorithm, Fama minimizes computational complexity, while its compact dual-mode point addition (PADD) unit significantly reduces hardware overhead. Compared to the best CPU-based design, Fama achieves over 184.20× speedup. It also outperforms state-of-the-art FPGA-based MSM accelerators, reducing resource overhead by more than 64% and boosting area-time product (ATP) by up to 37.09×.

Original language	English
Pages (from-to)	1867-1871
Number of pages	5
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	45
Issue number	4
DOIs	https://doi.org/10.1109/TCAD.2025.3608005
Publication status	Published - 1 Apr 2026
Externally published	Yes

Keywords

Field-programmable gate array (FPGA)
hardware accelerator
multiscalar multiplication (MSM)
zero-knowledge proof (ZKP)

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10.1109/TCAD.2025.3608005

Cite this

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title = "Fama: An FPGA-Oriented Multiscalar Multiplication Accelerator Optimized via Algorithm-Hardware Co-Design",

abstract = "Multiscalar multiplication (MSM) is the primary computational bottleneck in zero-knowledge proof (ZKP) protocols. To address this, we introduce Fama, a field-programmable gate array (FPGA)-oriented MSM accelerator developed through algorithm-hardware co-optimization. By integrating a 3D-Pippenger optimization algorithm, Fama minimizes computational complexity, while its compact dual-mode point addition (PADD) unit significantly reduces hardware overhead. Compared to the best CPU-based design, Fama achieves over 184.20× speedup. It also outperforms state-of-the-art FPGA-based MSM accelerators, reducing resource overhead by more than 64\% and boosting area-time product (ATP) by up to 37.09×.",

keywords = "Field-programmable gate array (FPGA), hardware accelerator, multiscalar multiplication (MSM), zero-knowledge proof (ZKP)",

author = "Yan Xu and Jingqi Zhang and Xiyan Dong and An Wang and Xinghua Wang and Liehuang Zhu",

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doi = "10.1109/TCAD.2025.3608005",

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AU - Dong, Xiyan

AU - Wang, An

AU - Wang, Xinghua

AU - Zhu, Liehuang

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AB - Multiscalar multiplication (MSM) is the primary computational bottleneck in zero-knowledge proof (ZKP) protocols. To address this, we introduce Fama, a field-programmable gate array (FPGA)-oriented MSM accelerator developed through algorithm-hardware co-optimization. By integrating a 3D-Pippenger optimization algorithm, Fama minimizes computational complexity, while its compact dual-mode point addition (PADD) unit significantly reduces hardware overhead. Compared to the best CPU-based design, Fama achieves over 184.20× speedup. It also outperforms state-of-the-art FPGA-based MSM accelerators, reducing resource overhead by more than 64% and boosting area-time product (ATP) by up to 37.09×.

KW - Field-programmable gate array (FPGA)

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Fama: An FPGA-Oriented Multiscalar Multiplication Accelerator Optimized via Algorithm-Hardware Co-Design

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Keywords

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