Fabrication and Characterizations of A Low-Warpage Interposer Embedded with Polyimide-liner TSVs for SIP Applications

Through-silicon-vias (TSVs) with polyimide (PI) liner have shown advantages in terms of small parasitic capacitance, good thermal-mechanical reliability, and low fabrication cost. However, their interposer-level properties such as the interposer warpage are still lacking. In this paper, a 2.0 cm × 1.5 cm interposer embedded with PI -liner TSV s is fabricated and characterized. Based on our reliable fabrication flow, TSVs with a diameter of 30 um and a depth of 200 um are suc-cessfully fabricated in a high yield of nearly 97%. The leakage current between a single TSV to the Si substrate is only 1.04 pA at 20 V, proving the good electrical performance of the fabricated TSV s. Besides, the maximum interposer-level warp-age after the double-sided chemical mechanical polishing (CMP) processes is only 17.5 urn and the local roughness of the polished substrate is below 24.8 nm. Such low-warpage inter-poser embedded with TSVs using low-k PI liner are promising for the advanced packaging technology and heterogeneous integration architecture including the system-in-package (SiP) applications.