Estimation and calibration for channel mismatches in high-speed ADC systems

Shaobo Jiao; Bo Yan; Liang Zhou; Zhiyong Guo

doi:10.1109/ICCCAS.2013.6765222

Estimation and calibration for channel mismatches in high-speed ADC systems

Shaobo Jiao, Bo Yan, Liang Zhou, Zhiyong Guo

University of Electronic Science and Technology of China

Research output: Contribution to conference › Paper › peer-review

1 Citation (Scopus)

Abstract

Since high-speed and high-resolution ADCs are needed in communication systems, single ADC can hardly achieve. This paper proposed a timing mismatch estimation and calibration algorithm in Time-Interleaved ADC (TIADC). A multistage differentiator-multiplier cascade (DMC) structure is disclosed for timing mismatch correction. As the present estimation and calibration method, the procedure can be performed without knowing input signal, and converges with smaller data samples. Finally, numerical simulations show that the proposed method can get good performance and Spurious Free Dynamic Range (SFDR) is improved significantly. The entire system can achieve 8 GHz and 8-bit resolution.

Original language	English
Pages	228-231
Number of pages	4
DOIs	https://doi.org/10.1109/ICCCAS.2013.6765222
Publication status	Published - 2013
Externally published	Yes
Event	2013 International Conference on Communications, Circuits and Systems, ICCCAS 2013 - Chengdu, China Duration: 15 Nov 2013 → 17 Nov 2013

Conference

Conference	2013 International Conference on Communications, Circuits and Systems, ICCCAS 2013
Country/Territory	China
City	Chengdu
Period	15/11/13 → 17/11/13

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10.1109/ICCCAS.2013.6765222

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title = "Estimation and calibration for channel mismatches in high-speed ADC systems",

abstract = "Since high-speed and high-resolution ADCs are needed in communication systems, single ADC can hardly achieve. This paper proposed a timing mismatch estimation and calibration algorithm in Time-Interleaved ADC (TIADC). A multistage differentiator-multiplier cascade (DMC) structure is disclosed for timing mismatch correction. As the present estimation and calibration method, the procedure can be performed without knowing input signal, and converges with smaller data samples. Finally, numerical simulations show that the proposed method can get good performance and Spurious Free Dynamic Range (SFDR) is improved significantly. The entire system can achieve 8 GHz and 8-bit resolution.",

author = "Shaobo Jiao and Bo Yan and Liang Zhou and Zhiyong Guo",

year = "2013",

doi = "10.1109/ICCCAS.2013.6765222",

language = "English",

pages = "228--231",

note = "2013 International Conference on Communications, Circuits and Systems, ICCCAS 2013 ; Conference date: 15-11-2013 Through 17-11-2013",

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TY - CONF

T1 - Estimation and calibration for channel mismatches in high-speed ADC systems

AU - Jiao, Shaobo

AU - Yan, Bo

AU - Zhou, Liang

AU - Guo, Zhiyong

PY - 2013

Y1 - 2013

N2 - Since high-speed and high-resolution ADCs are needed in communication systems, single ADC can hardly achieve. This paper proposed a timing mismatch estimation and calibration algorithm in Time-Interleaved ADC (TIADC). A multistage differentiator-multiplier cascade (DMC) structure is disclosed for timing mismatch correction. As the present estimation and calibration method, the procedure can be performed without knowing input signal, and converges with smaller data samples. Finally, numerical simulations show that the proposed method can get good performance and Spurious Free Dynamic Range (SFDR) is improved significantly. The entire system can achieve 8 GHz and 8-bit resolution.

AB - Since high-speed and high-resolution ADCs are needed in communication systems, single ADC can hardly achieve. This paper proposed a timing mismatch estimation and calibration algorithm in Time-Interleaved ADC (TIADC). A multistage differentiator-multiplier cascade (DMC) structure is disclosed for timing mismatch correction. As the present estimation and calibration method, the procedure can be performed without knowing input signal, and converges with smaller data samples. Finally, numerical simulations show that the proposed method can get good performance and Spurious Free Dynamic Range (SFDR) is improved significantly. The entire system can achieve 8 GHz and 8-bit resolution.

UR - http://www.scopus.com/inward/record.url?scp=84898822740&partnerID=8YFLogxK

U2 - 10.1109/ICCCAS.2013.6765222

DO - 10.1109/ICCCAS.2013.6765222

M3 - Paper

AN - SCOPUS:84898822740

SP - 228

EP - 231

T2 - 2013 International Conference on Communications, Circuits and Systems, ICCCAS 2013

Y2 - 15 November 2013 through 17 November 2013

ER -

Estimation and calibration for channel mismatches in high-speed ADC systems

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