Electronic Devices and System Integration in the Post-Moore Era

Peng Zhou; Mingrui Ao; Yutong Xiang; Chong Wang; Shaohua Fan; Qi Cheng Sun; Chunsen Liu; Jing Wan; Wenzhong Bao

doi:10.1109/IEDM50572.2025.11353651

Electronic Devices and System Integration in the Post-Moore Era

Peng Zhou^*
, Mingrui Ao
, Yutong Xiang
, Chong Wang
, Shaohua Fan
, Qi Cheng Sun
, Chunsen Liu^*
, Jing Wan^*
, Wenzhong Bao^*

^*Corresponding author for this work

Fudan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

As modern VLSI approaches scaling and power limits, two-dimensional (2D) materials offer new opportunities for advanced logic and memory integration. This work showcases major advances in 2D materials for next-generation VLSI, including 12-inch monolayer MoS₂ growth via CVD, a MoS₂ RISC-V WUJI processor with 99.92% transistor yield and inverter gain >550, and graphene-based flash PoX memory with sub-1 ns programming, 1.8 V window, and >10⁵ cycle endurance. These breakthroughs highlight the potential of 2D materials in logic, memory, and 2D-Si heterogeneous integration, enabling monolithic 3D architectures for energy-efficient, high-performance computing beyond Moore's Law.

Original language	English
Title of host publication	2025 IEEE International Electron Devices Meeting, IEDM 2025
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798331567859
DOIs	https://doi.org/10.1109/IEDM50572.2025.11353651
Publication status	Published - 2025
Externally published	Yes
Event	2025 IEEE International Electron Devices Meeting, IEDM 2025 - San Francisco, United States Duration: 6 Dec 2025 → 10 Dec 2025

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Conference

Conference	2025 IEEE International Electron Devices Meeting, IEDM 2025
Country/Territory	United States
City	San Francisco
Period	6/12/25 → 10/12/25

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10.1109/IEDM50572.2025.11353651

Cite this

Zhou, P., Ao, M., Xiang, Y., Wang, C., Fan, S., Sun, Q. C., Liu, C., Wan, J., & Bao, W. (2025). Electronic Devices and System Integration in the Post-Moore Era. In 2025 IEEE International Electron Devices Meeting, IEDM 2025 (Technical Digest - International Electron Devices Meeting, IEDM). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM50572.2025.11353651

@inproceedings{4b239390fd0146fc938f3eb255747bb6,

title = "Electronic Devices and System Integration in the Post-Moore Era",

abstract = "As modern VLSI approaches scaling and power limits, two-dimensional (2D) materials offer new opportunities for advanced logic and memory integration. This work showcases major advances in 2D materials for next-generation VLSI, including 12-inch monolayer MoS2 growth via CVD, a MoS2 RISC-V WUJI processor with 99.92\% transistor yield and inverter gain >550, and graphene-based flash PoX memory with sub-1 ns programming, 1.8 V window, and >105 cycle endurance. These breakthroughs highlight the potential of 2D materials in logic, memory, and 2D-Si heterogeneous integration, enabling monolithic 3D architectures for energy-efficient, high-performance computing beyond Moore's Law.",

author = "Peng Zhou and Mingrui Ao and Yutong Xiang and Chong Wang and Shaohua Fan and Sun, \{Qi Cheng\} and Chunsen Liu and Jing Wan and Wenzhong Bao",

note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 2025 IEEE International Electron Devices Meeting, IEDM 2025 ; Conference date: 06-12-2025 Through 10-12-2025",

year = "2025",

doi = "10.1109/IEDM50572.2025.11353651",

language = "English",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2025 IEEE International Electron Devices Meeting, IEDM 2025",

address = "United States",

}

Zhou, P, Ao, M, Xiang, Y, Wang, C, Fan, S, Sun, QC, Liu, C, Wan, J & Bao, W 2025, Electronic Devices and System Integration in the Post-Moore Era. in 2025 IEEE International Electron Devices Meeting, IEDM 2025. Technical Digest - International Electron Devices Meeting, IEDM, Institute of Electrical and Electronics Engineers Inc., 2025 IEEE International Electron Devices Meeting, IEDM 2025, San Francisco, United States, 6/12/25. https://doi.org/10.1109/IEDM50572.2025.11353651

Electronic Devices and System Integration in the Post-Moore Era. / Zhou, Peng; Ao, Mingrui; Xiang, Yutong et al.
2025 IEEE International Electron Devices Meeting, IEDM 2025. Institute of Electrical and Electronics Engineers Inc., 2025. (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Electronic Devices and System Integration in the Post-Moore Era

AU - Zhou, Peng

AU - Ao, Mingrui

AU - Xiang, Yutong

AU - Wang, Chong

AU - Fan, Shaohua

AU - Sun, Qi Cheng

AU - Liu, Chunsen

AU - Wan, Jing

AU - Bao, Wenzhong

PY - 2025

Y1 - 2025

N2 - As modern VLSI approaches scaling and power limits, two-dimensional (2D) materials offer new opportunities for advanced logic and memory integration. This work showcases major advances in 2D materials for next-generation VLSI, including 12-inch monolayer MoS2 growth via CVD, a MoS2 RISC-V WUJI processor with 99.92% transistor yield and inverter gain >550, and graphene-based flash PoX memory with sub-1 ns programming, 1.8 V window, and >105 cycle endurance. These breakthroughs highlight the potential of 2D materials in logic, memory, and 2D-Si heterogeneous integration, enabling monolithic 3D architectures for energy-efficient, high-performance computing beyond Moore's Law.

AB - As modern VLSI approaches scaling and power limits, two-dimensional (2D) materials offer new opportunities for advanced logic and memory integration. This work showcases major advances in 2D materials for next-generation VLSI, including 12-inch monolayer MoS2 growth via CVD, a MoS2 RISC-V WUJI processor with 99.92% transistor yield and inverter gain >550, and graphene-based flash PoX memory with sub-1 ns programming, 1.8 V window, and >105 cycle endurance. These breakthroughs highlight the potential of 2D materials in logic, memory, and 2D-Si heterogeneous integration, enabling monolithic 3D architectures for energy-efficient, high-performance computing beyond Moore's Law.

UR - https://www.scopus.com/pages/publications/105033523332

U2 - 10.1109/IEDM50572.2025.11353651

DO - 10.1109/IEDM50572.2025.11353651

M3 - Conference contribution

AN - SCOPUS:105033523332

T3 - Technical Digest - International Electron Devices Meeting, IEDM

BT - 2025 IEEE International Electron Devices Meeting, IEDM 2025

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2025 IEEE International Electron Devices Meeting, IEDM 2025

Y2 - 6 December 2025 through 10 December 2025

ER -

Electronic Devices and System Integration in the Post-Moore Era

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