Design of SAR Imaging System Based on MPSoC + FPGA with Optimization Strategies for Chirp Scaling Factor Computation

Space-based remote sensing involves complex SAR imaging hardware design. This complexity arises from varied imaging modes and a convoluted imaging process. With the rapid advancement of embedded systems and Field Programmable Gate Arrays (FPGA), underscores their flexibility, efficiency, and reconfigurability for SAR imaging hardware implementation. This paper introduces a comprehensive SAR imaging system based on Multi-Processor System on Chip (MPSoC) and FPGA architectures. The system supports a multi-modal SAR imaging processing platform with large granularity, encompassing orbital parameter pro-cessing, Chirp Scaling (CS) factor computation, data transposition, complex multiplication, and FFT operations. An effi-cient data link between the host computer, MPSoC, and FPGA is also established. To address the challenges of multiple parameters, intricate computational flow, and various computational types in Chirp Scaling factor generation, the system utilizes Cortex A53 and Cortex R5 processors for computation and optimization. The results indicate an average accelera-tion ratio of 25.296, a relative error of 1.12×10^-4, and an absolute error of 5.88×10^-6, demonstrating that the “MPSoC+FPGA”-based imaging system meets the demands of imaging processing.