TY - GEN
T1 - Design of FSM with concurrent error detection based on viterbi decoding
AU - Li, Ming
AU - Xu, Shiyi
AU - Xia, Enjun
AU - Wan, Fayu
PY - 2008
Y1 - 2008
N2 - In this paper a new technique for designing finite state machines with concurrent error detection is presented using convolutional codes. In order to correct the fault, we propose a novel scheme which can not only detect but also correct errors occurred in FSM transition. More specifically, we demonstrate how the checker using maximum likelihood decoding can correct single-bit error and get 3dB higher of asymptotic coding gain than previous techniques, also we analysts bit error rate performance for Viterbi decoding of convolutional code. Moreover, we realize the IP core of the self-checking module by SMIC 0.25μm CMOS technology and also simulate its function in FPGA.
AB - In this paper a new technique for designing finite state machines with concurrent error detection is presented using convolutional codes. In order to correct the fault, we propose a novel scheme which can not only detect but also correct errors occurred in FSM transition. More specifically, we demonstrate how the checker using maximum likelihood decoding can correct single-bit error and get 3dB higher of asymptotic coding gain than previous techniques, also we analysts bit error rate performance for Viterbi decoding of convolutional code. Moreover, we realize the IP core of the self-checking module by SMIC 0.25μm CMOS technology and also simulate its function in FPGA.
UR - https://www.scopus.com/pages/publications/58249114354
U2 - 10.1109/ATS.2008.20
DO - 10.1109/ATS.2008.20
M3 - Conference contribution
AN - SCOPUS:58249114354
SN - 9780769533964
T3 - Proceedings of the Asian Test Symposium
SP - 383
EP - 388
BT - Proceedings of the 17th Asian Test Symposium, ATS 2008
T2 - 17th Asian Test Symposium, ATS 2008
Y2 - 24 November 2008 through 27 November 2008
ER -