Design of decimation filter for real-time signal processing of micro-air-vehicles

  • Ying Tao Ding*
  • , Shun An Zhong
  • , Jing Chen
  • *Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper reports a digital decimation filter chip for real-time signal processing of micro-air-vehicles (MAVs), which is composed of cascade integrator comb (CIC) filter, half-band filter and CIC compensation filter. To obtain low power, low hardware cost and efficient area, optimization was performed at behavioral level modeling and register transfer level (RTL) design. A mathematical framework was presented to perform parameters optimization of different filters. The layout was designed based on SMIC 0.18 μ m process library. The verification results show that the chip achieves a signal to noise ratio (SNR) of 54.40dB. The chip area occupies 1.69mm 2 and dissipates only 2.95mW power. Area and power are well satisfied with the separation point detection of MAVs' boundary layer.

Original languageEnglish
Title of host publicationProceedings - 4th International Congress on Image and Signal Processing, CISP 2011
Pages2253-2256
Number of pages4
DOIs
Publication statusPublished - 2011
Event4th International Congress on Image and Signal Processing, CISP 2011 - Shanghai, China
Duration: 15 Oct 201117 Oct 2011

Publication series

NameProceedings - 4th International Congress on Image and Signal Processing, CISP 2011
Volume4

Conference

Conference4th International Congress on Image and Signal Processing, CISP 2011
Country/TerritoryChina
CityShanghai
Period15/10/1117/10/11

Keywords

  • decimation filter
  • low hardware cost
  • low power
  • real-time signal processing
  • separation point detection

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