TY - GEN
T1 - Design of a dynamically reconfigurable arithmetic unit for matrix algorithms
AU - Wang, Weijiang
AU - Ding, Yingtao
AU - Cao, Shan
AU - Zhao, Xianli
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2016/7/21
Y1 - 2016/7/21
N2 - Matrix operations, such as multiplication, inversion operations, are widely used in high-perforamce industrial control, scientific computing, and media processing applications. To meet the increasingly intensive timing and power demands of matrix opertions, dynamically reconfigurable structures are introduced as a new design paradigm to make a good balance between performance and flexibility. In this paper, a dynamically reconfigurable multi-operation arithmetic unit is proposed basing on multiply-add-fused unit. The proposed arithmetic unit consists of three pipeline stage, each of which can be dynamically configured by control signals. The proposed arithmetic unit can be used for addition, subtraction, multiplication and multiply-add-fused operations for different data types. Compared with the traditional arithmetic units, the chip area is reduced by the proposed unit since the most functional units are reused for different operations.
AB - Matrix operations, such as multiplication, inversion operations, are widely used in high-perforamce industrial control, scientific computing, and media processing applications. To meet the increasingly intensive timing and power demands of matrix opertions, dynamically reconfigurable structures are introduced as a new design paradigm to make a good balance between performance and flexibility. In this paper, a dynamically reconfigurable multi-operation arithmetic unit is proposed basing on multiply-add-fused unit. The proposed arithmetic unit consists of three pipeline stage, each of which can be dynamically configured by control signals. The proposed arithmetic unit can be used for addition, subtraction, multiplication and multiply-add-fused operations for different data types. Compared with the traditional arithmetic units, the chip area is reduced by the proposed unit since the most functional units are reused for different operations.
UR - https://www.scopus.com/pages/publications/84982311250
U2 - 10.1109/ASICON.2015.7516955
DO - 10.1109/ASICON.2015.7516955
M3 - Conference contribution
AN - SCOPUS:84982311250
T3 - Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
BT - Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
A2 - Ren, Junyan
A2 - Tang, Ting-Ao
A2 - Ye, Fan
A2 - Yu, Huihua
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
Y2 - 3 November 2015 through 6 November 2015
ER -