Design and realization of ultra high speed data acquisition system

Teng Long; Han Yueqiu; Erke Mao

Design and realization of ultra high speed data acquisition system

Teng Long^*, Han Yueqiu, Erke Mao

^*Corresponding author for this work

School of Information and Electronics

Beijing Institute of Technology

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

An ultra high speed data acquisition system is introduced, capable of performing 250 MS/s analog-digit conversion. The system employs data demulplexing architecture, microwave transmission line interconnection and multiple anti-jamming methods, enabling the system to have about 7 bit of ENOB even with 250 MS/s, 125 MHz signal input.

Original language	English
Pages (from-to)	147-150
Number of pages	4
Journal	Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology
Volume	15
Issue number	2
Publication status	Published - 1995

Keywords

Data acquisition
Emitter coupled logic circuits
High-speed A-D converters

Cite this

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title = "Design and realization of ultra high speed data acquisition system",

abstract = "An ultra high speed data acquisition system is introduced, capable of performing 250 MS/s analog-digit conversion. The system employs data demulplexing architecture, microwave transmission line interconnection and multiple anti-jamming methods, enabling the system to have about 7 bit of ENOB even with 250 MS/s, 125 MHz signal input.",

keywords = "Data acquisition, Emitter coupled logic circuits, High-speed A-D converters",

author = "Teng Long and Han Yueqiu and Erke Mao",

year = "1995",

language = "English",

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pages = "147--150",

journal = "Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology",

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publisher = "Beijing Institute of Technology",

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TY - JOUR

T1 - Design and realization of ultra high speed data acquisition system

AU - Long, Teng

AU - Yueqiu, Han

AU - Mao, Erke

PY - 1995

Y1 - 1995

N2 - An ultra high speed data acquisition system is introduced, capable of performing 250 MS/s analog-digit conversion. The system employs data demulplexing architecture, microwave transmission line interconnection and multiple anti-jamming methods, enabling the system to have about 7 bit of ENOB even with 250 MS/s, 125 MHz signal input.

AB - An ultra high speed data acquisition system is introduced, capable of performing 250 MS/s analog-digit conversion. The system employs data demulplexing architecture, microwave transmission line interconnection and multiple anti-jamming methods, enabling the system to have about 7 bit of ENOB even with 250 MS/s, 125 MHz signal input.

KW - Data acquisition

KW - Emitter coupled logic circuits

KW - High-speed A-D converters

UR - http://www.scopus.com/inward/record.url?scp=7744222935&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:7744222935

SN - 1001-0645

VL - 15

SP - 147

EP - 150

JO - Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology

JF - Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology

IS - 2

ER -

Design and realization of ultra high speed data acquisition system

Abstract

Keywords

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