Design and Optimization of High Speed PLL Based on 90 nm CMOS Process

Zheng Chen Wang; Xing Hua Wang; Shun An Zhong

doi:10.15918/j.tbit1001-0645.2018.01.010

Design and Optimization of High Speed PLL Based on 90 nm CMOS Process

Zheng Chen Wang, Xing Hua Wang^*, Shun An Zhong

^*Corresponding author for this work

School of Integrated Circuits and Electronics

Beijing Institute of Technology

Research output: Contribution to journal › Article › peer-review

Abstract

A high speed phase locked loop (PLL) was designed based on TSMC 90 nm CMOS process. In order to optimize phase noise and reference spur, the main modules of PLL such as charge pump and LC voltage controlled oscillator (VCO) were analyzed and improved. The design method of multi-modulus divider (MMD) was studied in detail. The layout of the high speed PLL was optimized and whole chip area was arranged in 490 μm×990 μm. The testing results show that, the in-band phase noise can reach -90 dBc at 1 MHz frequency offset and the reference spur is -56.797 dBc.

Original language	English
Pages (from-to)	58-62
Number of pages	5
Journal	Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology
Volume	38
Issue number	1
DOIs	https://doi.org/10.15918/j.tbit1001-0645.2018.01.010
Publication status	Published - 1 Jan 2018

Keywords

Charge pump
LC voltage controlled oscillator (VCO)
Phase noise
Phase-locked loop

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10.15918/j.tbit1001-0645.2018.01.010

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title = "Design and Optimization of High Speed PLL Based on 90 nm CMOS Process",

abstract = "A high speed phase locked loop (PLL) was designed based on TSMC 90 nm CMOS process. In order to optimize phase noise and reference spur, the main modules of PLL such as charge pump and LC voltage controlled oscillator (VCO) were analyzed and improved. The design method of multi-modulus divider (MMD) was studied in detail. The layout of the high speed PLL was optimized and whole chip area was arranged in 490 μm×990 μm. The testing results show that, the in-band phase noise can reach -90 dBc at 1 MHz frequency offset and the reference spur is -56.797 dBc.",

keywords = "Charge pump, LC voltage controlled oscillator (VCO), Phase noise, Phase-locked loop",

author = "Wang, \{Zheng Chen\} and Wang, \{Xing Hua\} and Zhong, \{Shun An\}",

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doi = "10.15918/j.tbit1001-0645.2018.01.010",

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TY - JOUR

T1 - Design and Optimization of High Speed PLL Based on 90 nm CMOS Process

AU - Wang, Zheng Chen

AU - Wang, Xing Hua

AU - Zhong, Shun An

PY - 2018/1/1

Y1 - 2018/1/1

N2 - A high speed phase locked loop (PLL) was designed based on TSMC 90 nm CMOS process. In order to optimize phase noise and reference spur, the main modules of PLL such as charge pump and LC voltage controlled oscillator (VCO) were analyzed and improved. The design method of multi-modulus divider (MMD) was studied in detail. The layout of the high speed PLL was optimized and whole chip area was arranged in 490 μm×990 μm. The testing results show that, the in-band phase noise can reach -90 dBc at 1 MHz frequency offset and the reference spur is -56.797 dBc.

AB - A high speed phase locked loop (PLL) was designed based on TSMC 90 nm CMOS process. In order to optimize phase noise and reference spur, the main modules of PLL such as charge pump and LC voltage controlled oscillator (VCO) were analyzed and improved. The design method of multi-modulus divider (MMD) was studied in detail. The layout of the high speed PLL was optimized and whole chip area was arranged in 490 μm×990 μm. The testing results show that, the in-band phase noise can reach -90 dBc at 1 MHz frequency offset and the reference spur is -56.797 dBc.

KW - Charge pump

KW - LC voltage controlled oscillator (VCO)

KW - Phase noise

KW - Phase-locked loop

UR - https://www.scopus.com/pages/publications/85047795460

U2 - 10.15918/j.tbit1001-0645.2018.01.010

DO - 10.15918/j.tbit1001-0645.2018.01.010

M3 - Article

AN - SCOPUS:85047795460

SN - 1001-0645

VL - 38

SP - 58

EP - 62

JO - Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology

JF - Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology

IS - 1

ER -

Design and Optimization of High Speed PLL Based on 90 nm CMOS Process

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Keywords

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