Design and optimization of dual modulus prescaler using the extended true-single-phase-clock

Chao Guo*, Siheng Zhu, Jun Hu, Jing Diao, Houjun Sun, Xin Lv

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Citations (Scopus)

Abstract

A low-power divide-by-4/5 unit of a prescaler is proposed. The power consumption and operating frequency of the extended true-single-phase-clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are analyzed. Compared with the existing design, a 20% reduction of power consumption is achieved. A divide-by-16/17 dual-modulus prescaler implemented with this divide-by-4/5 unit using a 0.18-um CMOS process is capable of operating up to 4.1 GHz with a low-power comsumpti-on. The prescaler is implemented in low-power high-resolution frequency dividers for wireless short distance application.

Original languageEnglish
Title of host publication2010 International Conference on Microwave and Millimeter Wave Technology, ICMMT 2010
Pages636-638
Number of pages3
DOIs
Publication statusPublished - 2010
Event2010 International Conference on Microwave and Millimeter Wave Technology, ICMMT 2010 - Chengdu, China
Duration: 8 May 201011 May 2010

Publication series

Name2010 International Conference on Microwave and Millimeter Wave Technology, ICMMT 2010

Conference

Conference2010 International Conference on Microwave and Millimeter Wave Technology, ICMMT 2010
Country/TerritoryChina
CityChengdu
Period8/05/1011/05/10

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