TY - GEN
T1 - Design and Implementation of Target Tracking System in Low Illumination Environment Based on FPGA
AU - Xin, Naijie
AU - Xie, Min
AU - Shi, Jian
AU - Lu, Tiantai
AU - Ma, Zhifeng
N1 - Publisher Copyright:
© 2023 ACM.
PY - 2023/3/24
Y1 - 2023/3/24
N2 - Object tracking has been an important research topic in the field of computer vision. At present, most target tracking algorithms need to work in an environment with good lighting conditions. Environments such as night, rainy days, and foggy days will cause tracking drift and even target loss. In order to solve the above problems, this design proposes a target tracking system that combines image enhancement algorithm and target tracking algorithm. The image enhancement uses the Multi-Scale Retinex (MSR) algorithm to correct the color and dynamic range of the input image; the target tracking algorithm uses the Meanshift algorithm to track the enhanced image. In order to deploy the algorithm to FPGA for edge computing acceleration, a streaming computing architecture is designed, and at the same time, the algorithm is partially refactored at the design level to better adapt to FPGA deployment; finally, high-level synthesis tools are used, combined with optimization instructions A high-efficiency target tracking system with local parallelization and overall pipeline is designed.
AB - Object tracking has been an important research topic in the field of computer vision. At present, most target tracking algorithms need to work in an environment with good lighting conditions. Environments such as night, rainy days, and foggy days will cause tracking drift and even target loss. In order to solve the above problems, this design proposes a target tracking system that combines image enhancement algorithm and target tracking algorithm. The image enhancement uses the Multi-Scale Retinex (MSR) algorithm to correct the color and dynamic range of the input image; the target tracking algorithm uses the Meanshift algorithm to track the enhanced image. In order to deploy the algorithm to FPGA for edge computing acceleration, a streaming computing architecture is designed, and at the same time, the algorithm is partially refactored at the design level to better adapt to FPGA deployment; finally, high-level synthesis tools are used, combined with optimization instructions A high-efficiency target tracking system with local parallelization and overall pipeline is designed.
KW - Algorithm Acceleration
KW - FPGA
KW - Image Enhancement
KW - Target Tracking
UR - http://www.scopus.com/inward/record.url?scp=85171292896&partnerID=8YFLogxK
U2 - 10.1145/3606193.3606199
DO - 10.1145/3606193.3606199
M3 - Conference contribution
AN - SCOPUS:85171292896
T3 - ACM International Conference Proceeding Series
SP - 31
EP - 37
BT - 2023 5th International Symposium on Signal Processing Systems, SSPS 2023
PB - Association for Computing Machinery
T2 - 5th International Symposium on Signal Processing Systems, SSPS 2023
Y2 - 24 March 2023 through 26 March 2023
ER -