TY - GEN
T1 - Design and Implementation of High-Speed Transmission Link Based on PCI-E
AU - Meng, Entong
AU - Bu, Xiangyuan
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/5
Y1 - 2020/5
N2 - In order to accomplish real-time control and monitor of high-speed acquisition system, reliable transmission of large-capacity data is in highly demand. In this article, a practical design of transmission link based on Rocket IO, PCI Express (PCI-E) and DDR3 is proposed. To counteract the data loss caused by PCI-E interrupts, large-capacity dynamic First Input First Output (FIFO) has been designed with the aid of DDR3. Cross-chip transmission link is introduced with the self-designed GTX/GTH interfaces. Besides, the design of PCI-E Direct Memory Access (DMA) mode is also demonstrated. Simulations and hardware tests are performed with the aid of Xilinx 7 series FPGAs to verify the practicality and reliability of the proposed transmission link. Quantitatively, data could be uploaded to user interface correctly at the rate of 6Gbps (approximating to the maximum rate of GTX when single lane is considered) without any loss, which means the adverse effect of PCI-E interrupts could be eradicated, and the transparent control and monitor of high-speed acquisition system could be realized with the aid of the proposed transmission link.
AB - In order to accomplish real-time control and monitor of high-speed acquisition system, reliable transmission of large-capacity data is in highly demand. In this article, a practical design of transmission link based on Rocket IO, PCI Express (PCI-E) and DDR3 is proposed. To counteract the data loss caused by PCI-E interrupts, large-capacity dynamic First Input First Output (FIFO) has been designed with the aid of DDR3. Cross-chip transmission link is introduced with the self-designed GTX/GTH interfaces. Besides, the design of PCI-E Direct Memory Access (DMA) mode is also demonstrated. Simulations and hardware tests are performed with the aid of Xilinx 7 series FPGAs to verify the practicality and reliability of the proposed transmission link. Quantitatively, data could be uploaded to user interface correctly at the rate of 6Gbps (approximating to the maximum rate of GTX when single lane is considered) without any loss, which means the adverse effect of PCI-E interrupts could be eradicated, and the transparent control and monitor of high-speed acquisition system could be realized with the aid of the proposed transmission link.
KW - DDR3
KW - DMA
KW - PCI-E
KW - Rocket IO
KW - dynamic FIFO
KW - high-speed acquisition system
UR - http://www.scopus.com/inward/record.url?scp=85087720380&partnerID=8YFLogxK
U2 - 10.1109/ICTC49638.2020.9123289
DO - 10.1109/ICTC49638.2020.9123289
M3 - Conference contribution
AN - SCOPUS:85087720380
T3 - 2020 Information Communication Technologies Conference, ICTC 2020
SP - 188
EP - 191
BT - 2020 Information Communication Technologies Conference, ICTC 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2020 Information Communication Technologies Conference, ICTC 2020
Y2 - 29 May 2020 through 31 May 2020
ER -