Design and Implementation of CNN Accelerator Based on FPGA

As one of the important research directions in the field of computer vision, CNN based object detection methods are constantly being updated, which puts higher requirements on the computational performance of hardware acceleration platforms. FPGA achieves a balance between acceleration performance, power consumption, and configurability, making it a good compromise for hardware accelerator platform options. Based on this, this paper implements a FPGA-based CNN accelerator with certain universality by designing universal operators. This paper mainly uses ping-pong buffer mechanism to optimize the loading of parameters and data and at the same time uses pipeline to optimize the calculation. Based on the concept of reverse positioning and sequence calculation, the operator is designed to achieve weight reuse and output feature map calculation. YOLOv4-Tiny is built on ZYNQ7020 for verification, which has an acceleration ratio of 1162 compared to using only the ARM processor and has an energy efficiency ratio of 2.847GOPS/W compared to GPU's 2.311GOPS/W.