Design and implementation of an improved channelized architechture

When complex signals go through poly-phase digital channelized receiver, in order to ensure there are no blind spots and frequency aliasing, the maximum decimation factor per channel can only be half of the number of the channels. In this way, the entire receiver has to process at least twice as much data as before. This directly sets much higher requirements to the processing rate of signal processors. What is more, the sampling rate of analog-to-digital converter today is far beyond the processing rate of signal processor. With the expectation to fill the gap between the processing rate of signal processor and the sampling rate of DAC, this paper developed a parallel computing architecture. This method analyses the law of the convolution in the non-blind spots digital channelized receiver and the filter bank structure is achieved by using two modules. Besides, this design ameliorates the source problem of processors efficiently by adopting parallel computing on multi-processors. Experimental results proved that the proposed method performs well in improving the characteristic of ultra-wideband channelized receiver, especially complex signals involved. & copy; 2009 IEEE.