Design and implementation of an AMBA-based radar signal processing IP

Aiming at the IP reusable design methodology based on the standard on-chip bus, which is the key of on-chip radar system design, a design of radar signal processing IP based on AMBA2.0 AHB Lite is presented, in which digital down convert and digital pulse compression are completed. The IP structure and the child modules design are introduced, and the IP prototype is verified on ARM versatile PB926EJ-S platform. The compression output in 32 bit IEEE754 floating-point or block-floating-point format can be achieved in 73.31 μs for 1024 point DPC or 15.84 μs for 256 point DPC. The result shows that the IP design is successful and can be applied to construct high-speed on-chip radar signal system rapidly.