TY - GEN
T1 - Design and implementation of a 1.5Gsps digital channelized receiver
AU - Xu, Shichao
AU - Liu, Guoman
AU - Gao, Meiguo
AU - Jie, Qinguo
PY - 2010
Y1 - 2010
N2 - Based on the derivation of the efficient implementation structure of the frequency domain polyphase filter digital channelized receiver, a digital channelized receiver was achieved on the hardware platform with I/Q sampling, 1500Msps, 64channels. In order to ensure good performance of the system, optimization of the processor speed and processor resources was fully considered during the design process of the whole system. The actual ultra-wideband signal test results show that the digital channelized receiver is in good performance.
AB - Based on the derivation of the efficient implementation structure of the frequency domain polyphase filter digital channelized receiver, a digital channelized receiver was achieved on the hardware platform with I/Q sampling, 1500Msps, 64channels. In order to ensure good performance of the system, optimization of the processor speed and processor resources was fully considered during the design process of the whole system. The actual ultra-wideband signal test results show that the digital channelized receiver is in good performance.
KW - Complex signal
KW - Digital channelized receiver
KW - High speed
KW - Poly-phase filter
UR - https://www.scopus.com/pages/publications/79951667740
U2 - 10.1109/ICIECS.2010.5677721
DO - 10.1109/ICIECS.2010.5677721
M3 - Conference contribution
AN - SCOPUS:79951667740
SN - 9781424479412
T3 - 2nd International Conference on Information Engineering and Computer Science - Proceedings, ICIECS 2010
BT - 2nd International Conference on Information Engineering and Computer Science - Proceedings, ICIECS 2010
T2 - 2nd International Conference on Information Engineering and Computer Science, ICIECS 2010
Y2 - 25 December 2010 through 26 December 2010
ER -