COMRANCE: A rapid method for Network-on-Chip design space exploration

Mingzhe Zhang, Yangguang Shi, Fa Zhang, Zhiyong Liu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Citations (Scopus)

Abstract

As the communication sub-system that connecting various on-chip components, Network-on-Chip (NoC) has a great influence on the performance of multi-/many-core processors. Because of NoC model contains a large number of parameters, the design space exploration (DSE) for NoC is a critical problem for the architects. Similar to the core design, existing DSE process mainly depends on iteratively time-consuming simulations. To lower the time budget, many previous studies focus on reducing the simulations. However, most of the proposed works based on regression or machine learning techniques, whose accuracy will be significantly affected by the scale of training set. It still needs a lot of simulations to build the training set.

Original languageEnglish
Title of host publication2016 7th International Green and Sustainable Computing Conference, IGSC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509051175
DOIs
Publication statusPublished - 4 Apr 2017
Externally publishedYes
Event7th International Green and Sustainable Computing Conference, IGSC 2016 - Hangzhou, China
Duration: 7 Aug 20169 Nov 2016

Publication series

Name2016 7th International Green and Sustainable Computing Conference, IGSC 2016

Conference

Conference7th International Green and Sustainable Computing Conference, IGSC 2016
Country/TerritoryChina
CityHangzhou
Period7/08/169/11/16

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