Co-SEC: An Adaptive Security-Enhanced ASCON Accelerator via Algorithm-Hardware Co-Design

Yan Xu; Jingqi Zhang; Jianbo Guo; Jiakun Li; An Wang; Liehuang Zhu

doi:10.1109/TCSII.2026.3716290

Co-SEC: An Adaptive Security-Enhanced ASCON Accelerator via Algorithm-Hardware Co-Design

Yan Xu
, Jingqi Zhang^*
, Jianbo Guo
, Jiakun Li
, An Wang
, Liehuang Zhu

^*Corresponding author for this work

Hunan University
Beijing Institute of Technology
Hefei University of Technology
Shandong Provincial Key Laboratory of Energy Industry Internet Big Data Technology

Research output: Contribution to journal › Article › peer-review

Abstract

Internet of Things (IoT) devices in open environments are vulnerable to physical attacks on their cryptographic keys, while facing diverse and ever-changing application requirements. To address these issues, this paper proposes CO-SEC, an adaptive and security enhanced ASCON accelerator. CO-SEC integrates a physical unclonable function (PUF) to provide secondary encryption for the original key to thwart physical attacks. Furthermore, by introducing a folding factor and leveraging algorithm-hardware co-design, CO-SEC realizes an adaptively parameterized, run-time reconfigurable dataflow, thereby achieving hardware adaptability across different IoT application scenarios. Experimental results show that CO-SEC achieves a throughput improvement of 1.55-7.57× while maintaining key security above 99.99%.

Original language	English
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
DOIs	https://doi.org/10.1109/TCSII.2026.3716290
Publication status	Accepted/In press - 2026
Externally published	Yes

Keywords

ASCON
FPGA
Hardware Accelerator
Lightweight Cryptography
Physical Unclonable Function (PUF)

Access to Document

10.1109/TCSII.2026.3716290

Cite this

@article{c25bbe6238a04a0680f52b5b5bd801f5,

title = "Co-SEC: An Adaptive Security-Enhanced ASCON Accelerator via Algorithm-Hardware Co-Design",

abstract = "Internet of Things (IoT) devices in open environments are vulnerable to physical attacks on their cryptographic keys, while facing diverse and ever-changing application requirements. To address these issues, this paper proposes CO-SEC, an adaptive and security enhanced ASCON accelerator. CO-SEC integrates a physical unclonable function (PUF) to provide secondary encryption for the original key to thwart physical attacks. Furthermore, by introducing a folding factor and leveraging algorithm-hardware co-design, CO-SEC realizes an adaptively parameterized, run-time reconfigurable dataflow, thereby achieving hardware adaptability across different IoT application scenarios. Experimental results show that CO-SEC achieves a throughput improvement of 1.55-7.57{\texttimes} while maintaining key security above 99.99\%.",

keywords = "ASCON, FPGA, Hardware Accelerator, Lightweight Cryptography, Physical Unclonable Function (PUF)",

author = "Yan Xu and Jingqi Zhang and Jianbo Guo and Jiakun Li and An Wang and Liehuang Zhu",

note = "Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

year = "2026",

doi = "10.1109/TCSII.2026.3716290",

language = "English",

journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",

issn = "1549-7747",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - Co-SEC

T2 - An Adaptive Security-Enhanced ASCON Accelerator via Algorithm-Hardware Co-Design

AU - Xu, Yan

AU - Zhang, Jingqi

AU - Guo, Jianbo

AU - Li, Jiakun

AU - Wang, An

AU - Zhu, Liehuang

PY - 2026

Y1 - 2026

N2 - Internet of Things (IoT) devices in open environments are vulnerable to physical attacks on their cryptographic keys, while facing diverse and ever-changing application requirements. To address these issues, this paper proposes CO-SEC, an adaptive and security enhanced ASCON accelerator. CO-SEC integrates a physical unclonable function (PUF) to provide secondary encryption for the original key to thwart physical attacks. Furthermore, by introducing a folding factor and leveraging algorithm-hardware co-design, CO-SEC realizes an adaptively parameterized, run-time reconfigurable dataflow, thereby achieving hardware adaptability across different IoT application scenarios. Experimental results show that CO-SEC achieves a throughput improvement of 1.55-7.57× while maintaining key security above 99.99%.

AB - Internet of Things (IoT) devices in open environments are vulnerable to physical attacks on their cryptographic keys, while facing diverse and ever-changing application requirements. To address these issues, this paper proposes CO-SEC, an adaptive and security enhanced ASCON accelerator. CO-SEC integrates a physical unclonable function (PUF) to provide secondary encryption for the original key to thwart physical attacks. Furthermore, by introducing a folding factor and leveraging algorithm-hardware co-design, CO-SEC realizes an adaptively parameterized, run-time reconfigurable dataflow, thereby achieving hardware adaptability across different IoT application scenarios. Experimental results show that CO-SEC achieves a throughput improvement of 1.55-7.57× while maintaining key security above 99.99%.

KW - ASCON

KW - FPGA

KW - Hardware Accelerator

KW - Lightweight Cryptography

KW - Physical Unclonable Function (PUF)

UR - https://www.scopus.com/pages/publications/105045984231

U2 - 10.1109/TCSII.2026.3716290

DO - 10.1109/TCSII.2026.3716290

M3 - Article

AN - SCOPUS:105045984231

SN - 1549-7747

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

ER -

Co-SEC: An Adaptive Security-Enhanced ASCON Accelerator via Algorithm-Hardware Co-Design

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Cite this