Calibration of gain and time mismatches for time-interleaved ADCs based on digital filter bank

Wen Jun Shi*, Bo Yan

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Citation (Scopus)

Abstract

As we known, time-interleaved analog-to-digital converters (TIADC) is effective on increasing the system sampling rate. But the gain, offset and time mismatches among the sub-ADCs introduce undesirable noise into the system and degrade the overall performance seriously. This paper describes a post calibration method with digital filter banks to remove the gain and time mismatch errors. These digital filters, whose coefficients are according to weighted least square (WLS) criteria, are carried out with poly-phase structure. Simulation results show that this method can significantly improve the spurious free dynamic range (SFDR) and signal to noise ratio (SNR) of TIADC system.

Original languageEnglish
Title of host publicationProceedings 2011 International Conference on Mechatronic Science, Electric Engineering and Computer, MEC 2011
Pages1836-1839
Number of pages4
DOIs
Publication statusPublished - 2011
Externally publishedYes
Event2011 International Conference on Mechatronic Science, Electric Engineering and Computer, MEC 2011 - Jilin, China
Duration: 19 Aug 201122 Aug 2011

Publication series

NameProceedings 2011 International Conference on Mechatronic Science, Electric Engineering and Computer, MEC 2011

Conference

Conference2011 International Conference on Mechatronic Science, Electric Engineering and Computer, MEC 2011
Country/TerritoryChina
CityJilin
Period19/08/1122/08/11

Keywords

  • digital filter bank
  • polyphase structure
  • time interleaved analog to digital converter
  • time skew mismatch

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