Built-in-self-test-stacked 3-D ring oscillator based on through silicon vias

A 3-D ring oscillator integrated with through silicon vias (TSVs) is designed and fabricated for testing multilayer-stacked integrated circuits (ICs) with TSV. The proposed 3-D ring oscillator consists of 13 stages and 65-nm Complementary Metal-Oxide-Semiconductor Transistor (CMOS) dies with two current-starved inverters and via-last TSVs designed for the five middle layers of the 3-D ring oscillator. The two cascaded inverters are connected to the upside layer through a TSV and to the downside layer through a microbump. One chip with two inverters but without TSV is stacked in the top layer of the 3-D ring oscillator to realize the ring oscillator loop, and one logic chip with one inverter and via-middle TSVs are in the bottom of the ring oscillator. The characteristics of via-last and via-middle TSVs in the 3-D ring oscillator are analyzed based on the equivalent circuits. The oscillation frequency responses of the designed 3-D ring oscillator are measured finally to verify the design concept, and to assess the performance of the 3-D ring oscillator. The measured results demonstrate that the proposed 3-D ring oscillator is an attractive candidate for testing the stacked 3-D IC, and the effect of TSVs dominates the delay of the 3-D ring oscillator.