AN EXTREMELY PIPELINED FPGA-BASED ACCELERATOR FOR SAR SATELLITE ON-BOARD REAL-TIME PROCESSING

Directly implementing intelligent real-time processing on the satellite can effectively reduce data processing latency and alleviate communication burdens. Existing convolution neural networks (CNNs) typically have a huge magnitude of parameters and intensive computation, making it a challenge to deploy CNN-based models onboard. To resolve this issue, this paper proposes an extremely pipelined FPGA-based accelerator with both algorithm and hardware optimization for SAR satellite on-board real-time processing. Firstly, in order to reduce the hardware resource overhead, convolution kernel weights and activations are quantized to signed and unsigned integers respectively, lightening the pressure of computing resource overhead. Secondly, a multi-level data prefetching strategy is proposed to optimize the data flow and resource consumption, making it possible to eliminate expensive off-chip memory access. Finally, an accelerator that computes all layers in simultaneous pipeline is proposed, significantly reducing the latency of data processing. Extensive experiments conducted on AMD-Xilinx XC7VX690T FPGA board show that the mAP reaches 93.5% on SSDD dataset while the throughput of the accelerator achieves 1.72 tera operation per second (TOPS) with 15.302W in 200MHz, demonstrating the capability of proposed accelerator for real-time processing.