An efficient vlsi architecture and implementation of motion compensation for video decoder

Chao Cao*, Li Zhen Yu, Yanjun Zhang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Motion compensation calculation of video decoder frequently access the video data which are stored in external memory, thus efficient memory access is critical in the design of decoder. An advanced parallel multi-pipe line architecture of Motion compensation is proposed in this paper, which fulfilled different of picture prediction modes employed by multi standard video decoder. In this architecture, buffering mechanism for the reference data is used to reduce external memory access, and DMA is used to control data transformation between modules. Compared with traditional memory fetch module, the proposed architecture reduces 30%~40% video decoding cycle in H.264 decoding. Synthetically result shows that timing and the area of this design are both satisfied the requirement of video decoder.

Original languageEnglish
Title of host publicationCommunications and Information Processing - International Conference, ICCIP 2012, Revised Selected Papers
Pages556-563
Number of pages8
EditionPART 2
DOIs
Publication statusPublished - 2012
Event2012 International Conference on Communications and Information Processing, ICCIP 2012 - Aveiro, Portugal
Duration: 7 Mar 201211 Mar 2012

Publication series

NameCommunications in Computer and Information Science
NumberPART 2
Volume289 CCIS
ISSN (Print)1865-0929

Conference

Conference2012 International Conference on Communications and Information Processing, ICCIP 2012
Country/TerritoryPortugal
CityAveiro
Period7/03/1211/03/12

Keywords

  • component
  • Motion Compensation
  • Reference data fetch
  • Video decoder

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