An 81.5dB-DR 1.25MHz-BW VCO-Based CT ΔΣ ADC with Double-PFD Quantizer

In the IoT era, VCO-based Δ Σ ADCs are showing growing popularity due to its highly digital architecture, thus allowing analog circuits to harness process scaling for low power, high speed, and high precision [1-6]. In such ADCs, the VCO integrates the voltage input into phase output, followed by the phase quantizer for digitization. To boost VCO-based ADC's energy efficiency, the high resolution and wide detection range phase quantizers are highly desired. However, current implementations still have limitations. For an N-stage dual VCO, the conventional XOR-based phase quantizer only detects the phase difference between 0 and π without the lead-lag information, leading to a small detecting range and low resolution of N [1]. A phase-extended quantizer (PEQ) [2], [4] extracts the lead-lag information, thus expanding the detection range from-π to π and improving resolution to 2N. However, its lead-lag extraction requires accessing all output nodes of the VCO, largely increasing the circuit complexity and power. By detecting the rising edge of the dual VCO's outputs in each oscillation cycle, the PFD-based phase quantizer naturally extracts the lead-lag status and ensures full range (-2 π to 2 π) detection of the VCO phase information [3]. However, due to its single-edge detection, its phase resolution is limited to 2N. Additionally, the prior PFD-based quantizer suffers from 2X gain reduction.