An 8-bit 4.8-GS/s Four-Channel Time-Interleaved SAR ADC With Ping-Pong Comparators Using Global-Dither-Based Timing-Skew Calibration and Bit-Distribution-Based Offset Calibration

This article presents a global-dither-based timing-skew calibration technique for time-interleaved (TI) analog-to-digital converters (ADCs). By injecting a dithered reference signal globally at the input buffer, the proposed method ensures negligible residual timing skews after calibration. A dither-injection scheme based on source-follower (SF) addition is proposed to suppress the dither kickback and enable a single-tap dither-removal mechanism. In addition, a bit-distribution-based offset calibration method is introduced to support high-speed successive-approximation-register (SAR) ADCs employing ping-pong comparators without an additional calibration phase. Fabricated in a 28-nm CMOS process, a prototype 8-bit 4.8-GS/s four-channel TI SAR ADC achieves 44.3-dB SNDR and 58.2-dB SFDR at Nyquist. The ADC consumes 10.4 mW and achieves a Walden figure of merit (FoM) of 16.2 fJ/conv-step, including the input buffer and the on-chip calibration engine, demonstrating the effectiveness of the proposed background calibration techniques for high-speed TI SAR ADCs.