A Wire-bonded Multichip SiC Power Module with Low Parasitic Inductance and High Current Sharing Characteristic

In this paper, a low parasitic inductance, high current sharing characteristic, wire-bonded multichip SiC power module was designed, fabricated, and tested. This paper proposes a novel DBC layout to reduce the parasitic inductances and improve the current sharing characteristics by using the multiloop method. The performances of both the commercial module and the proposed module are compared through simulation. In the simulation, the power loop inductance of proposed module is reduced to 2.36 nH, which is only 46% of the commercial module. At the same time, due to the highly symmetrical layout, better current sharing characteristics have been achieved in the proposed module, with a maximum turn-on current difference of only 1.78A. To validate the analysis and designs, a 1200V 6mΩ SiC half-bridge power module is designed, fabricated, and tested. The double pulse test results show that the power loop inductance of the proposed module is about 3.04nH, and the maximum difference in current peak is about 3.07A, which indicates that the proposed module has good performance.