A Study on Thickness-Dependent Performances of High-k Gated Tellurium-Based Field-Effect Transistors

Yang Hui Xia; Zi Chun Liu; Shu Ming Qi; Yu Hang Zheng; Yu Meng Wang; Xiao Long Xu; Hui Xia Yang; Yuan Xiao Ma; Yeliang Wang

doi:10.1109/EDSSC64492.2025.11183255

A Study on Thickness-Dependent Performances of High-k Gated Tellurium-Based Field-Effect Transistors

Yang Hui Xia
, Zi Chun Liu
, Shu Ming Qi
, Yu Hang Zheng
, Yu Meng Wang
, Xiao Long Xu
, Hui Xia Yang^*
, Yuan Xiao Ma^*
, Yeliang Wang^*

^*Corresponding author for this work

Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this work, p-type tellurium-based field-effect transistors (Te-FETs) have been successfully fabricated. A mixture high-k HfLaO is developed as gate dielectric in replacement of the traditional SiO2 to enhance the field effect, lowering the operation voltage from -50 V to -8 V for a high power efficiency. Moreover, the Te channel film is readily thinned by shortening the deposition duration from 90 seconds to 20 seconds. This can suppress off-state current due to the reduced amount of hole carriers in a thinner film. Furthermore, a lowtemperature annealing (∼ 150°C) is adopted to additionally decline the off-state current because Te content can be decreased by oxygen compensation during the annealing in air, diminishing hole carriers. Interestingly, the on-state current is concurrently promoted, which should result from the atomic rearrangement by absorbing sufficient thermal energy during the annealing, improving the quality of Te film and Te/HfLaO interface. As a result, the on/off ratio of the annealed device has been successfully improved about 10 times as compared to the pristine device.

Original language	English
Title of host publication	Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	142-143
Number of pages	2
ISBN (Electronic)	9798331522087
DOIs	https://doi.org/10.1109/EDSSC64492.2025.11183255
Publication status	Published - 2025
Externally published	Yes
Event	16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025 - Yinchuan, China Duration: 13 Jun 2025 → 15 Jun 2025

Publication series

Name	Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025

Conference

Conference	16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025
Country/Territory	China
City	Yinchuan
Period	13/06/25 → 15/06/25

Keywords

annealing treatment
high-k dielectric
Te-FETs

Access to Document

10.1109/EDSSC64492.2025.11183255

Cite this

Xia, Y. H., Liu, Z. C., Qi, S. M., Zheng, Y. H., Wang, Y. M., Xu, X. L., Yang, H. X., Ma, Y. X., & Wang, Y. (2025). A Study on Thickness-Dependent Performances of High-k Gated Tellurium-Based Field-Effect Transistors. In Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025 (pp. 142-143). (Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC64492.2025.11183255

Xia, Yang Hui ; Liu, Zi Chun ; Qi, Shu Ming et al. / A Study on Thickness-Dependent Performances of High-k Gated Tellurium-Based Field-Effect Transistors. Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025. Institute of Electrical and Electronics Engineers Inc., 2025. pp. 142-143 (Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025).

@inproceedings{e27468cdb4ed48548a1e7a84dfe0aa70,

title = "A Study on Thickness-Dependent Performances of High-k Gated Tellurium-Based Field-Effect Transistors",

abstract = "In this work, p-type tellurium-based field-effect transistors (Te-FETs) have been successfully fabricated. A mixture high-k HfLaO is developed as gate dielectric in replacement of the traditional SiO2 to enhance the field effect, lowering the operation voltage from -50 V to -8 V for a high power efficiency. Moreover, the Te channel film is readily thinned by shortening the deposition duration from 90 seconds to 20 seconds. This can suppress off-state current due to the reduced amount of hole carriers in a thinner film. Furthermore, a lowtemperature annealing (∼ 150°C) is adopted to additionally decline the off-state current because Te content can be decreased by oxygen compensation during the annealing in air, diminishing hole carriers. Interestingly, the on-state current is concurrently promoted, which should result from the atomic rearrangement by absorbing sufficient thermal energy during the annealing, improving the quality of Te film and Te/HfLaO interface. As a result, the on/off ratio of the annealed device has been successfully improved about 10 times as compared to the pristine device.",

keywords = "annealing treatment, high-k dielectric, Te-FETs",

author = "Xia, \{Yang Hui\} and Liu, \{Zi Chun\} and Qi, \{Shu Ming\} and Zheng, \{Yu Hang\} and Wang, \{Yu Meng\} and Xu, \{Xiao Long\} and Yang, \{Hui Xia\} and Ma, \{Yuan Xiao\} and Yeliang Wang",

note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025 ; Conference date: 13-06-2025 Through 15-06-2025",

year = "2025",

doi = "10.1109/EDSSC64492.2025.11183255",

language = "English",

series = "Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "142--143",

booktitle = "Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025",

address = "United States",

}

Xia, YH, Liu, ZC, Qi, SM, Zheng, YH, Wang, YM, Xu, XL, Yang, HX, Ma, YX & Wang, Y 2025, A Study on Thickness-Dependent Performances of High-k Gated Tellurium-Based Field-Effect Transistors. in Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025. Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025, Institute of Electrical and Electronics Engineers Inc., pp. 142-143, 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025, Yinchuan, China, 13/06/25. https://doi.org/10.1109/EDSSC64492.2025.11183255

A Study on Thickness-Dependent Performances of High-k Gated Tellurium-Based Field-Effect Transistors. / Xia, Yang Hui; Liu, Zi Chun; Qi, Shu Ming et al.
Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025. Institute of Electrical and Electronics Engineers Inc., 2025. p. 142-143 (Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A Study on Thickness-Dependent Performances of High-k Gated Tellurium-Based Field-Effect Transistors

AU - Xia, Yang Hui

AU - Liu, Zi Chun

AU - Qi, Shu Ming

AU - Zheng, Yu Hang

AU - Wang, Yu Meng

AU - Xu, Xiao Long

AU - Yang, Hui Xia

AU - Ma, Yuan Xiao

AU - Wang, Yeliang

PY - 2025

Y1 - 2025

N2 - In this work, p-type tellurium-based field-effect transistors (Te-FETs) have been successfully fabricated. A mixture high-k HfLaO is developed as gate dielectric in replacement of the traditional SiO2 to enhance the field effect, lowering the operation voltage from -50 V to -8 V for a high power efficiency. Moreover, the Te channel film is readily thinned by shortening the deposition duration from 90 seconds to 20 seconds. This can suppress off-state current due to the reduced amount of hole carriers in a thinner film. Furthermore, a lowtemperature annealing (∼ 150°C) is adopted to additionally decline the off-state current because Te content can be decreased by oxygen compensation during the annealing in air, diminishing hole carriers. Interestingly, the on-state current is concurrently promoted, which should result from the atomic rearrangement by absorbing sufficient thermal energy during the annealing, improving the quality of Te film and Te/HfLaO interface. As a result, the on/off ratio of the annealed device has been successfully improved about 10 times as compared to the pristine device.

AB - In this work, p-type tellurium-based field-effect transistors (Te-FETs) have been successfully fabricated. A mixture high-k HfLaO is developed as gate dielectric in replacement of the traditional SiO2 to enhance the field effect, lowering the operation voltage from -50 V to -8 V for a high power efficiency. Moreover, the Te channel film is readily thinned by shortening the deposition duration from 90 seconds to 20 seconds. This can suppress off-state current due to the reduced amount of hole carriers in a thinner film. Furthermore, a lowtemperature annealing (∼ 150°C) is adopted to additionally decline the off-state current because Te content can be decreased by oxygen compensation during the annealing in air, diminishing hole carriers. Interestingly, the on-state current is concurrently promoted, which should result from the atomic rearrangement by absorbing sufficient thermal energy during the annealing, improving the quality of Te film and Te/HfLaO interface. As a result, the on/off ratio of the annealed device has been successfully improved about 10 times as compared to the pristine device.

KW - annealing treatment

KW - high-k dielectric

KW - Te-FETs

UR - https://www.scopus.com/pages/publications/105019960210

U2 - 10.1109/EDSSC64492.2025.11183255

DO - 10.1109/EDSSC64492.2025.11183255

M3 - Conference contribution

AN - SCOPUS:105019960210

T3 - Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025

SP - 142

EP - 143

BT - Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025

Y2 - 13 June 2025 through 15 June 2025

ER -

Xia YH, Liu ZC, Qi SM, Zheng YH, Wang YM, Xu XL et al. A Study on Thickness-Dependent Performances of High-k Gated Tellurium-Based Field-Effect Transistors. In Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025. Institute of Electrical and Electronics Engineers Inc. 2025. p. 142-143. (Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025). doi: 10.1109/EDSSC64492.2025.11183255

A Study on Thickness-Dependent Performances of High-k Gated Tellurium-Based Field-Effect Transistors

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Keywords

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