A Study on Short-Circuit Parasitic Conduction Failure of 1200 V SiC VDMOSFETs

In this study, the parasitic conduction failure of typical 1200 V SiC VDMOSFETs under short-circuit conditions have been systematically investigated. Based on experimental and simulation results, the mechanism of parasitic conduction failure during short-circuit events is elucidated. The device operates in saturation mode when a short circuit occurs, during which current flows through the channel, JFET region, and N-drift region to cause a significant heating. As a result, the parasitic npn transistor is triggered as the temperature rises, leading to a second current rise and resultant thermal failure. Accordingly, a Multi-pillar structure featuring four pillars with various depths (0.5 ∼ 0.2 μ m) beneath the p-well region is proposed to mitigate the parasitic conduction failure. As verified by simulation, the peak short-circuit current is reduced by 3.16%, and the shortcircuit withstand time (SCWT) is increased by 18.18%. This Multi-pillar structure partially blocks parasitic current path and inhibits the activation of the parasitic transistor.