A stress-insensitive arrayed capacitive MEMS accelerometer

Aiming at the performance degradation of capacitive MEMS accelerometers caused by environmental stress and temperature drift, this paper proposes a highly robust design method featuring the co-optimization of "structure, packaging, and algorithm." The accelerometer employs a 2 × 2 array of single-anchor subunits and stepped-height comb-finger structures to reduce its intrinsic stress sensitivity. This is combined with a rectangular center-chip adhesive pattern and a stress-partitioning compensation strategy to systematically enhance its environmental stability. The device is fabricated and wafer-level packaged using a self-aligned SOI process. Mechanical stress and temperature test results demonstrate that, after optimization, the accelerometer's bias stress drift is reduced by approximately 74.02% and its sensitivity stress drift by about 66.53%; its bias temperature drift is reduced by roughly 62.72% and its sensitivity temperature drift by about 89.54%. Furthermore, the device exhibits a nonlinearity of 788 ppm within the ±1 g range, a noise floor of 12.93 μg/√Hz, and a bias instability of 10.25 μg, indicating excellent overall performance. This research provides an effective co-design paradigm for high-performance inertial sensors, which can be extended to other stress-sensitive MEMS devices.