@inproceedings{e1a8daf39e4a42568da236de8429438f,
title = "A Second-Order VCO-Based ΔΣ ADC with Fully Digital Feedback Summation",
abstract = "This paper presents a second-order VCO-based \textbackslash{}Delta\textbackslash{}Sigma ADC with a fully digital feedback adder, which is highly digital, area efficient and low power. Both the first and second loop integrator are implemented by VCOs and are free of OTA. A novel digital adder is proposed to realize the secondary feedback, significantly reducing the power and area of the second stage. The proposed ADC is designed in a 28nm CMOS technology under 0.9V supply, consuming only 1.14mW. The simulated SNDR and SFDR are 72.5dB and 84.1dB respectively over a 5MHz signal bandwidth.",
keywords = "ADC, Delta-Sigma, Scaling-friendly, Time-domain, VCO-based",
author = "Chaoyang Xing and Yi Zhong and Jin Shao and Pengpeng Chen and Lu Jie and Nan Sun",
note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022 ; Conference date: 27-05-2022 Through 01-06-2022",
year = "2022",
doi = "10.1109/ISCAS48785.2022.9937991",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "3215--3218",
booktitle = "IEEE International Symposium on Circuits and Systems, ISCAS 2022",
address = "United States",
}