A scaleable DSP system for ASIP design

Zhang Yanjun; He Hu; Zhou Zhixiong; Yang Xu; Sun Yihe

doi:10.1109/ASSCC.2006.357889

A scaleable DSP system for ASIP design

Zhang Yanjun^*
, He Hu
, Zhou Zhixiong
, Yang Xu
, Sun Yihe

^*Corresponding author for this work

Tsinghua University

Research output: Contribution to conference › Paper › peer-review

1 Citation (Scopus)

Abstract

This paper describes a scaleable DSP architecture for ASIP design and a retargetable compiler based on ORC. By configuring this architecture, designers can easily get the ASIP for one set of applications. A DSP named THUASDSP2004 is developed manually based on this architecture and the compiler can give a satisfied result.

Original language	English
Pages	215-218
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2006.357889
Publication status	Published - 2006
Externally published	Yes
Event	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China Duration: 13 Nov 2006 → 15 Nov 2006

Conference

Conference	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006
Country/Territory	China
City	Hangzhou
Period	13/11/06 → 15/11/06

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10.1109/ASSCC.2006.357889

Cite this

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title = "A scaleable DSP system for ASIP design",

abstract = "This paper describes a scaleable DSP architecture for ASIP design and a retargetable compiler based on ORC. By configuring this architecture, designers can easily get the ASIP for one set of applications. A DSP named THUASDSP2004 is developed manually based on this architecture and the compiler can give a satisfied result.",

author = "Zhang Yanjun and He Hu and Zhou Zhixiong and Yang Xu and Sun Yihe",

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doi = "10.1109/ASSCC.2006.357889",

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AU - Yanjun, Zhang

AU - Hu, He

AU - Zhixiong, Zhou

AU - Xu, Yang

AU - Yihe, Sun

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N2 - This paper describes a scaleable DSP architecture for ASIP design and a retargetable compiler based on ORC. By configuring this architecture, designers can easily get the ASIP for one set of applications. A DSP named THUASDSP2004 is developed manually based on this architecture and the compiler can give a satisfied result.

AB - This paper describes a scaleable DSP architecture for ASIP design and a retargetable compiler based on ORC. By configuring this architecture, designers can easily get the ASIP for one set of applications. A DSP named THUASDSP2004 is developed manually based on this architecture and the compiler can give a satisfied result.

UR - https://www.scopus.com/pages/publications/34250803329

U2 - 10.1109/ASSCC.2006.357889

DO - 10.1109/ASSCC.2006.357889

M3 - Paper

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EP - 218

T2 - 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006

Y2 - 13 November 2006 through 15 November 2006

ER -

A scaleable DSP system for ASIP design

Abstract

Conference

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