Abstract
This letter presents the design and fabrication of a through-silicon-via (TSV) structure using ultra-low-resistivity-silicon (ULRS) as the central conductor and air-gap as the insulation layer. Silicon-Air-silicon (SAS) TSVs are successfully fabricated using a simple and low-cost fabrication process based on a novel double-side half-Annular Si etching technique. A comparative study on different overlapping areas of the double-side Si etching is carried out to guarantee the proper formation of the air-gap insulation layer and to minimize the lateral undercutting effect occurred near the openings of the air-gaps. Thanks to the good isolation nature of the air and the successful formation of the air-gaps, we have achieved a capacitance density of 0.137 nF/cm2 and a leakage current density of 3.85 nA/cm2 for a single SAS TSV, indicating superior electrical properties in terms of ultra-low parasitic capacitance and excellent insulating performance, which shows an alluring prospect in future 3-D integration strategies and applications.
Original language | English |
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Article number | 9171906 |
Pages (from-to) | 1544-1547 |
Number of pages | 4 |
Journal | IEEE Electron Device Letters |
Volume | 41 |
Issue number | 10 |
DOIs | |
Publication status | Published - Oct 2020 |
Keywords
- 3-D integration
- Air-gap
- low capacitance
- silicon-Air-silicon
- through-silicon-via