A novel low-overhead fault tolerant parallel-pipelined FFT design

Yu Xie; Chen Yang; Chuang An Mao; He Chen; Yi Zhuang Xie

doi:10.1109/DFT.2017.8244461

A novel low-overhead fault tolerant parallel-pipelined FFT design

Yu Xie, Chen Yang, Chuang An Mao, He Chen^*, Yi Zhuang Xie

^*Corresponding author for this work

School of Information and Electronics

Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Citations (Scopus)

Abstract

As soft errors become a significant threat to modern electronic systems, the first priority of protection against soft errors should be decreasing resource consumption. This brief proposes a novel low-overhead fault tolerant FFT design, combining modified reduced precision redundancy (RPR) method and error correction codes (ECCs). RPR can lower the hardware overhead when compared with traditional full-precision redundancy techniques, especially when resource of the original design is huge. ECCs are cost-efficient for achieving fault tolerance on our parallel-pipelined FFT. As an example, an FPGA implementation of a four-channel 16K-point FFT is presented, which demonstrates that the proposed scheme can further reduce the overhead of fault tolerance designs.

Original language	English
Title of host publication	2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-4
Number of pages	4
ISBN (Electronic)	9781538603628
DOIs	https://doi.org/10.1109/DFT.2017.8244461
Publication status	Published - 28 Jun 2017
Event	13th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017 - Cambridge, United Kingdom Duration: 23 Oct 2017 → 25 Oct 2017

Publication series

Name	2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017
Volume	2018-January

Conference

Conference	13th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017
Country/Territory	United Kingdom
City	Cambridge
Period	23/10/17 → 25/10/17

Keywords

ECCs
FFT
FPGA
RPR
fault tolerant

Access to Document

10.1109/DFT.2017.8244461

Cite this

Xie, Y., Yang, C., Mao, C. A., Chen, H., & Xie, Y. Z. (2017). A novel low-overhead fault tolerant parallel-pipelined FFT design. In 2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017 (pp. 1-4). (2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017; Vol. 2018-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFT.2017.8244461

Xie, Yu ; Yang, Chen ; Mao, Chuang An et al. / A novel low-overhead fault tolerant parallel-pipelined FFT design. 2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 1-4 (2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017).

@inproceedings{76107cd8e56545e1a32d3a8e44b46ecb,

title = "A novel low-overhead fault tolerant parallel-pipelined FFT design",

abstract = "As soft errors become a significant threat to modern electronic systems, the first priority of protection against soft errors should be decreasing resource consumption. This brief proposes a novel low-overhead fault tolerant FFT design, combining modified reduced precision redundancy (RPR) method and error correction codes (ECCs). RPR can lower the hardware overhead when compared with traditional full-precision redundancy techniques, especially when resource of the original design is huge. ECCs are cost-efficient for achieving fault tolerance on our parallel-pipelined FFT. As an example, an FPGA implementation of a four-channel 16K-point FFT is presented, which demonstrates that the proposed scheme can further reduce the overhead of fault tolerance designs.",

keywords = "ECCs, FFT, FPGA, RPR, fault tolerant",

author = "Yu Xie and Chen Yang and Mao, {Chuang An} and He Chen and Xie, {Yi Zhuang}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 13th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017 ; Conference date: 23-10-2017 Through 25-10-2017",

year = "2017",

month = jun,

day = "28",

doi = "10.1109/DFT.2017.8244461",

language = "English",

series = "2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1--4",

booktitle = "2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017",

address = "United States",

}

Xie, Y, Yang, C, Mao, CA, Chen, H & Xie, YZ 2017, A novel low-overhead fault tolerant parallel-pipelined FFT design. in 2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017. 2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017, vol. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 1-4, 13th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017, Cambridge, United Kingdom, 23/10/17. https://doi.org/10.1109/DFT.2017.8244461

A novel low-overhead fault tolerant parallel-pipelined FFT design. / Xie, Yu; Yang, Chen; Mao, Chuang An et al.
2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 1-4 (2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017; Vol. 2018-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A novel low-overhead fault tolerant parallel-pipelined FFT design

AU - Xie, Yu

AU - Yang, Chen

AU - Mao, Chuang An

AU - Chen, He

AU - Xie, Yi Zhuang

PY - 2017/6/28

Y1 - 2017/6/28

N2 - As soft errors become a significant threat to modern electronic systems, the first priority of protection against soft errors should be decreasing resource consumption. This brief proposes a novel low-overhead fault tolerant FFT design, combining modified reduced precision redundancy (RPR) method and error correction codes (ECCs). RPR can lower the hardware overhead when compared with traditional full-precision redundancy techniques, especially when resource of the original design is huge. ECCs are cost-efficient for achieving fault tolerance on our parallel-pipelined FFT. As an example, an FPGA implementation of a four-channel 16K-point FFT is presented, which demonstrates that the proposed scheme can further reduce the overhead of fault tolerance designs.

AB - As soft errors become a significant threat to modern electronic systems, the first priority of protection against soft errors should be decreasing resource consumption. This brief proposes a novel low-overhead fault tolerant FFT design, combining modified reduced precision redundancy (RPR) method and error correction codes (ECCs). RPR can lower the hardware overhead when compared with traditional full-precision redundancy techniques, especially when resource of the original design is huge. ECCs are cost-efficient for achieving fault tolerance on our parallel-pipelined FFT. As an example, an FPGA implementation of a four-channel 16K-point FFT is presented, which demonstrates that the proposed scheme can further reduce the overhead of fault tolerance designs.

KW - ECCs

KW - FFT

KW - FPGA

KW - RPR

KW - fault tolerant

UR - http://www.scopus.com/inward/record.url?scp=85046028005&partnerID=8YFLogxK

U2 - 10.1109/DFT.2017.8244461

DO - 10.1109/DFT.2017.8244461

M3 - Conference contribution

AN - SCOPUS:85046028005

T3 - 2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017

SP - 1

EP - 4

BT - 2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 13th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017

Y2 - 23 October 2017 through 25 October 2017

ER -

Xie Y, Yang C, Mao CA, Chen H , Xie YZ. A novel low-overhead fault tolerant parallel-pipelined FFT design. In 2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 1-4. (2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017). doi: 10.1109/DFT.2017.8244461

A novel low-overhead fault tolerant parallel-pipelined FFT design

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