@inproceedings{4686b34048944e3caedc0c8ee6ad155f,
title = "A method of verification in chisel based deep learning accelerator design",
abstract = "Chisel is a new generation of hardware construction language (HCL) for agile development. More and more developers have developed their project in agile design. At the same time, a considerable part of Verilog-based design has also been released in agile design versions. However, there is no comprehensive verification flow for Chisel based design. Due to the difficulties of verification in Chisel based design, it is a tough task to attach Chisel based design on Verilog based design. We purpose a feasible verification flow in chisel-based deep learning accelerator (DLA) design, which is composed by performance equivalence check at module-level and function equivalence check at pin-level. Compared to Universe Verification Method in RTL level codes that cost considerable time and funds, this verification flow improves the verification efficiency and reduce the difficulty of debug.",
keywords = "Chisel, Deep learning accelerator, Verification",
author = "Zhinan Li and Yijie Chen and Di Zhao",
note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 IEEE International Conference on Information Technology, Big Data and Artificial Intelligence, ICIBA 2020 ; Conference date: 06-11-2020 Through 08-11-2020",
year = "2020",
month = nov,
day = "6",
doi = "10.1109/ICIBA50161.2020.9277284",
language = "English",
series = "Proceedings of 2020 IEEE International Conference on Information Technology, Big Data and Artificial Intelligence, ICIBA 2020",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "789--792",
editor = "Bing Xu and Kefen Mou",
booktitle = "Proceedings of 2020 IEEE International Conference on Information Technology, Big Data and Artificial Intelligence, ICIBA 2020",
address = "United States",
}